LDPC Parity Check Matrix Layout for Faster Rate-Compatible Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current wireless communication systems face challenges in efficiently decoding and encoding data due to errors and noise, particularly in high-speed data transmission and storage, where existing LDPC codes struggle with complexity and performance in multi-access technologies like 5G NR, leading to delays and inefficiencies in error correction.
Innovation Solution
The implementation of a parity check matrix with row orthogonality in LDPC decoding and encoding, specifically designed for lifted LDPC codes, which allows for efficient processing by ensuring that each pair of consecutive rows connected to punctured variable nodes are orthogonal, reducing processing delays and improving decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional LDPC codes are used for high-speed data transmission, then data rate is improved, but decoding complexity and processing delays increase
Solution Approach 1:
The parity check matrix is segmented into multiple blocks, where each block corresponds to a specific rate-compatible LDPC code. This segmentation allows the decoder to process different code rates using dedicated matrix blocks, reducing overall decoding complexity while maintaining high data transmission rates.
Solution Approach 2:
The parity check matrix is pre-processed to ensure row orthogonality between consecutive rows before decoding operations. This preliminary arrangement of the matrix structure enables more efficient decoding algorithms that can operate faster with reduced computational complexity.
2Reliability
If conventional LDPC codes are used for error correction, then reliability is improved, but processing delays increase
Solution Approach 1:
Row orthogonality is pre-established in the parity check matrix structure, which enables the decoder to immediately access up-to-date variable check sums without additional processing delays. This preliminary structural arrangement maintains error correction reliability while reducing processing time.
Solution Approach 2:
The patent replaces complex iterative decoding mechanisms with a more efficient structure that utilizes the pre-established row orthogonality property. This substitution reduces the number of computational steps required while maintaining the same error correction performance.
3Adaptability or versatility
If rate-compatible LDPC codes are implemented, then adaptability is improved, but decoding efficiency deteriorates
Solution Approach 1:
The parity check matrix is divided into multiple rate-compatible blocks, where each block can be independently processed. This segmentation maintains adaptability across different code rates while improving decoding efficiency through localized processing that avoids unnecessary computations.
Solution Approach 2:
Each block of the parity check matrix is designed with specific local properties optimized for its designated code rate. This local optimization ensures that decoding operations are performed with maximum efficiency for each specific rate while maintaining overall system adaptability.
Data Source
AI summary
Certain aspects of the present disclosure generally relate to methods and apparatus for decoding low-density parity check (LDPC) codes, for example, using a parity check matrix having full row-orthogonality. An exemplary method for performing low-density parity-check (LDPC) decoding includes receiving soft bits associated to an LDPC codeword and performing LDPC decoding of the soft bits using a parity check matrix, wherein each row of the parity check matrix corresponds to a lifted parity check of a lifted LDPC code, at least two columns of the parity check matrix correspond to punctured variable nodes of the lifted LDPC code, and the parity check matrix has row orthogonality between each pair of consecutive rows that are below a row to which the at least two punctured variable nodes are both connected.