LDPC Parity-Check Matrix Rotation for Flexible High-Throughput Coding
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Solution Overview
Problem
Current low-density parity check (LDPC) codes in wireless communication systems face challenges in achieving high throughput with efficient hardware utilization, particularly in supporting a wide range of information block lengths and code rates, especially in next-generation networks like 5G New Radio.
Innovation Solution
The method involves rotating the parity-check matrix using shift registers, where each shift register cyclically shifts its set of bits by an individual shift amount less than or equal to a maximum shift amount per cycle, and outputs rotated bits when the shift corresponds to an element in the parity-check matrix, enabling efficient LDPC coding and decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If LDPC codes are implemented to support a wide range of information block lengths and code rates, then the adaptability is improved, but the device complexity increases
Solution Approach 1:
The patent implements dynamic configuration of the parity-check matrix through incremental rotation, where the rotation amount is adjusted based on the specific code rate and block length requirements. This allows the same hardware structure to adapt to different communication scenarios without requiring multiple dedicated hardware configurations, thereby resolving the contradiction between adaptability and device complexity.
Solution Approach 2:
The patent changes the rotation parameter of the parity-check matrix dynamically according to different code rates and block lengths. By modifying the rotation amount parameter, the system can support various LDPC code configurations using a single hardware architecture, thus achieving high adaptability without increasing device complexity.
2Productivity
If incremental parity-check matrix rotation is performed using multiple shift registers, then the productivity is improved, but the device complexity increases
Solution Approach 1:
The patent divides the parity-check matrix rotation operation into multiple independent shift registers, each handling a specific column or set of columns. This segmentation allows parallel processing of different parts of the matrix, significantly improving throughput while keeping each individual shift register component simple and manageable.
Solution Approach 2:
The shift registers are designed to perform multiple functions: they can hold different sets of bits corresponding to different columns, perform incremental rotation by controlled amounts, and output rotated bits when the shift corresponds to matrix elements. This multi-functionality reduces the need for separate dedicated hardware for each operation, improving productivity without proportionally increasing device complexity.
3Ease of operation
If the maximum shift amount per cycle is limited to reduce complexity, then the ease of operation is improved, but the loss of time increases
Solution Approach 1:
The patent employs periodic incremental rotation where the shift amount is applied in regular cycles rather than as a single large operation. Each cycle performs a controlled shift within the maximum limit, and multiple cycles together achieve the total required rotation. This periodic approach maintains ease of operation while reducing overall latency through parallel processing and efficient resource utilization.
Solution Approach 2:
The shift registers continuously perform useful work by rotating bits incrementally in each cycle without idle periods. The controlled maximum shift amount ensures manageable complexity while the continuous operation across multiple cycles achieves the complete rotation efficiently, minimizing time loss despite the step-by-step approach.
Data Source
AI summary
Aspects of the present disclosure relate to parity-check matrix (P-matrix) rotation in low-density parity check (LDPC) coding. The P-matrix rotation may be performed by a plurality of shift registers, where each shift register is configured to receive a respective set of bits corresponding to a respective column in the P-matrix. Each cycle, the shift registers may then incrementally rotate their respective sets of bits to achieve a respective shift amount up to a maximum shift amount per cycle. During a cycle, if the shift amount produced by a shift register results in a degree of rotation corresponding to an element within the respective column of the P-matrix, the shift register may output the rotated set of bits for further processing.