LDPC Matrix Selective Merge for Low-Latency BP Decoding
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Solution Overview
Problem
Current communication systems employing LDPC codes face challenges in achieving low signal-to-noise ratios (SNR) required for error-free data transmission, particularly in high-data-rate communications, where traditional concatenated codes incur latency constraints, limiting their applicability.
Innovation Solution
The development of selective merge and partial reuse methods for constructing LDPC codes, specifically using Belief Propagation (BP) decoding with a limited number of layers, allows for efficient LDPC code construction and decoding, optimizing sub-matrix sizes and reuse patterns to achieve near-capacity performance in communication systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional concatenated codes are used to achieve error-free transmission, then reliability is improved, but latency increases and data rate is limited
Solution Approach 1:
The patent changes the fundamental parameters of error correction by transitioning from traditional concatenated codes to LDPC codes with specific degree distributions. This parameter change enables the system to achieve near-Shannon-limit performance with lower latency, as LDPC codes allow for parallel decoding operations unlike the sequential nature of concatenated codes
Solution Approach 2:
The patent employs dynamic degree distribution profiles for the LDPC code construction, where different variable nodes have different degrees (number of connections). This dynamic structure allows the decoder to process multiple bits simultaneously in parallel, reducing latency while maintaining high reliability, unlike static traditional codes
2Reliability
If LDPC codes with large code length are used to approach Shannon limit, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent segments the large LDPC code into smaller sub-matrices with specific structures (circulant sub-matrices). This segmentation allows the decoder to process the code in manageable blocks, reducing memory requirements and computational complexity while maintaining the ability to approach the Shannon limit through proper sub-matrix design and connectivity patterns
Solution Approach 2:
The patent applies local quality by creating non-uniform degree distributions where different parts of the code have different properties. Specifically, variable nodes have different degrees and check nodes have different degrees, creating localized structures that optimize decoding performance. This local variation allows the system to achieve near-Shannon-limit performance without requiring uniformly complex structures throughout the entire code
3Reliability
If irregular LDPC codes with specific degree distributions are used, then decoding performance is improved, but code construction complexity increases
Solution Approach 1:
The patent performs preliminary action by pre-defining specific degree distribution profiles and sub-matrix structures before code construction. The degree distributions for variable nodes and check nodes are determined in advance based on target performance requirements, and these pre-determined parameters guide the systematic construction of the LDPC matrix, reducing the complexity of the construction process while ensuring optimal decoding performance
Solution Approach 2:
The patent uses copying by creating multiple LDPC codes with different rate profiles from a single base code structure. By systematically modifying the degree distributions and sub-matrix patterns of a parent code, the invention generates a family of codes with different rates (e.g., 1/2, 2/3, 3/4) that all inherit the optimized structure, reducing construction complexity compared to designing each code from scratch
Data Source
AI summary
Selective merge and partial reuse LDPC (Low Density Parity Check) code construction for limited number of layers Belief Propagation (BP) decoding. Multiple LDPC matrices may be generated from a base code, such that multiple/distinct LDPC coded signals may be encoded and/or decoded within a singular communication device. Generally speaking, a first LDPC matrix is modified in accordance with one or more operations thereby generating a second LDPC matrix, and the second LDPC matrix is employed in accordance with encoding an information bit thereby generating an LDPC coded signal (alternatively performed using an LDPC generator matrix corresponding to the LDPC matrix) and/or decoding processing of an LDPC coded signal thereby generating an estimate of an information bit encoded therein. The operations performed on the first LDPC matrix may be any one of, or combination of, selectively merging, deleting, partially re-using one or more sub-matrix rows, and/or partitioning sub-matrix rows.