QC-LDPC Parity Check Matrix Encoding for Short-Block Latency
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Solution Overview
Problem
Existing LDPC encoding methods in wireless communication systems face challenges in reducing latency for short blocks with relatively short lengths, which is crucial for supporting wide coverage in 5G communication.
Innovation Solution
The proposed method employs a parity check matrix of an LDPC code optimized for reducing latency in transmitting short blocks. This is achieved by using a quasi-cyclic LDPC code structure, where the parity check matrix is generated based on a characteristic matrix and a lifting value, allowing for efficient encoding and decoding processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional LDPC encoding methods are used, then encoding can be performed with standard complexity, but latency in transmitting short blocks is high
Solution Approach 1:
The parity check matrix is divided into multiple sub-matrices, where each sub-matrix corresponds to a specific code rate. This segmentation allows the encoder to quickly identify and use the appropriate sub-matrix for the given code rate, avoiding the need to process the entire large matrix and thereby reducing latency for short blocks while maintaining manageable complexity through modular structure
Solution Approach 2:
The parity check matrix is pre-structured with sub-matrices arranged in a specific pattern where each sub-matrix is designed for a particular code rate. This preliminary organization enables the encoding process to directly access the required sub-matrix without dynamic computation or reconfiguration, significantly reducing latency while the fixed structure keeps encoding complexity predictable and controllable
2Adaptability or versatility
If LDPC code supports wide coverage of data transmission from 20 Gbps to a few tens of bps, then various code rates must be supported, but encoding complexity increases
Solution Approach 1:
The parity check matrix is designed as a universal structure where multiple sub-matrices within the same matrix can serve different code rate requirements. This multi-functional design allows a single parity check matrix to support a wide range of code rates from high (20 Gbps) to low (tens of bps), providing adaptability without requiring separate encoding mechanisms for each code rate, thus avoiding exponential complexity increase
Solution Approach 2:
Different sub-matrices within the parity check matrix are designed with locally optimized properties suitable for specific code rates. Each sub-matrix has tailored characteristics that make it efficient for its designated code rate range, allowing the overall system to achieve high adaptability across wide bandwidths while keeping the complexity of each local encoding operation manageable and specialized
Data Source
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AI summary
A method for performing encoding on the basis of a parity check matrix of a low density parity check code according to the present embodiment comprises the steps of: generating a parity check matrix by a terminal, wherein the parity check matrix corresponds to a characteristic matrix, each component of the characteristic matrix corresponds to a shift index value determined through a modulo operation between a corresponding component in a basic matrix and Zc, which is a lifting value, and the basic matrix is a 42 x 52 matrix; and performing encoding of input data, by the terminal, using the parity check matrix, wherein the lifting value is associated with the length of the input data.