LDPC Code Matrix Sub-Structure for Hardware Complexity Reduction
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Solution Overview
Problem
Existing LDPC code decoding technologies face challenges in efficiently encoding and decoding due to the high memory requirements for storing parity-check matrices, which complicates hardware implementation and increases computational complexity.
Innovation Solution
The proposed solution involves generating and using a parity-check matrix composed of square sub-matrices with unique values on each row and column, allowing for parallel processing and simplifying the decoding process by dividing the information word into block matrices and performing cyclic shifts, thereby reducing memory size and computational complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional parity-check matrix is used for LDPC code decoding, then decoding accuracy is maintained, but memory size and hardware complexity increase significantly
Solution Approach 1:
The parity-check matrix is divided into multiple sub-matrices, each representing a specific pattern type. This segmentation allows the decoder to process different sub-matrices using specialized, simplified hardware units rather than a general-purpose complex decoder, thereby reducing overall hardware complexity while maintaining decoding accuracy.
Solution Approach 2:
The invention changes the representation parameters of the parity-check matrix by encoding it in terms of sub-matrix patterns and their positions rather than storing the complete dense matrix. This parameter transformation reduces the memory footprint from O(N×M) to O(K×L) where K and L are the numbers of sub-matrices and pattern types, respectively.
2Loss of information
If a conventional parity-check matrix is stored in memory, then complete code information is available, but memory size increases
Solution Approach 1:
Instead of storing the complete parity-check matrix, the invention stores compressed representations (sub-matrix patterns) that can be algorithmically expanded during decoding. This copying approach uses minimal memory to store pattern definitions that replicate the full matrix information when needed, reducing memory size from storing all N×M elements to storing only the essential pattern descriptors.
3Reliability
If standard decoding algorithms are used, then decoding performance is maintained, but processing speed decreases
Solution Approach 1:
The decoding process is segmented into parallel operations on different sub-matrices. Each sub-matrix can be processed independently or in parallel, enabling pipelined and concurrent execution of decoding algorithms. This segmentation transforms a sequential bottleneck into a parallel processing architecture, significantly improving processing speed while maintaining decoding performance.
Solution Approach 2:
The parity-check matrix is pre-processed into sub-matrix patterns during code design, and these patterns are stored for rapid lookup during decoding. This preliminary organization of data eliminates the need for complex real-time matrix manipulations during the actual decoding process, thereby accelerating processing speed without compromising performance.
Data Source
AI summary
An LDPC code encoding apparatus includes: a code matrix generator for generating and transmitting a parity-check matrix comprising a combination of square matrices having a unique value on each row and column thereof; an encoding means encoding block LDPC codes according to the parity-check matrix received from the code matrix generator; and a codeword selector for puncturing the encoded result of the encoding means to generate an LDPC codeword. The code matrix generator divides an information word to be encoded into block matrices having a predetermined length to generate a vector information word. The encoding means encodes the block LDPC codes using the parity-check matrix divided into the block matrices and a Tanner graph divided into smaller graphs in correspondence to the parity-check matrix.