LDPC Decoder Memory Banking for Parallel Check-Node Processing
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Solution Overview
Problem
High-speed optical communication systems face challenges in data transmission rates due to optical phenomena like chromatic dispersion and polarization mode dispersion, which limit the ability of receivers to demodulate and decode signals, and existing FEC schemes, such as LDPC codes, suffer from latency issues in iterative decoding processes.
Innovation Solution
An LDPC decoder architecture that supports parallel processing of check nodes using an edge memory with independent banks for extrinsic information storage and processing, allowing concurrent access to double the number of check nodes without increasing memory size, and utilizing incremental changes to update extrinsic information during decoding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the number of check nodes processed in parallel is increased to improve decoding speed, then productivity is improved, but device complexity increases due to larger memory requirements
Solution Approach 1:
The edge memory is divided into multiple independent banks, where each bank can be accessed simultaneously by different processing units. This segmentation allows multiple check nodes to be processed in parallel while keeping each memory bank at a manageable size, thus increasing decoding speed without proportionally increasing total memory capacity.
Solution Approach 2:
The patent transitions from a single-dimension memory access model to a multi-dimensional model by organizing memory into banks that can be accessed concurrently. This dimensional change in memory architecture enables parallel processing of multiple check nodes while maintaining efficient memory utilization.
2Reliability
If iterative decoding is used to improve error correction capability, then reliability is improved, but loss of time increases due to multiple decoding iterations
Solution Approach 1:
The memory architecture is pre-configured with multiple independent banks that are ready for simultaneous access. This preliminary organization of memory resources enables the decoding process to perform multiple iterations more efficiently by reducing memory access bottlenecks, thus maintaining high reliability while reducing the time penalty associated with iterative decoding.
Data Source
AI summary
Methods, systems, and devices are described for decoding data using a low-density parity check (LDPC) decoder. An edge memory in the LDPC decoder is configured to have a first bank and a second bank of memory partitions. The first bank stores extrinsic information for edges for a first set of N check nodes and the second bank stores extrinsic information for edges for a second set of N check nodes. The first and second banks are concurrently accessed to process 2N check nodes in parallel. The first and second sets of N check nodes may respectively correspond to odd-numbered and even-numbered check nodes from the 2N check nodes processed in parallel by the LDPC decoder. The LDPC decoder operation may include initializing channel soft information into a memory different from the edge memory and the use of incremental changes in the extrinsic information to update the extrinsic information.