LDPC Decoder Memory Banking for Pseudo Two-Port Throughput
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Solution Overview
Problem
Conventional decoders face challenges in increasing modulation and reducing burst durations without significant increases in area and power consumption, as they typically require larger and more expensive dual port memory devices or increased clock speed, which can be impractical for devices with space limitations.
Innovation Solution
The solution involves configuring a single port memory device as a pseudo two port memory device by using a single port even bank and a single port odd bank, with a controller generating an access table to enable simultaneous reading and writing operations, effectively reducing processing time and maintaining device size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If dual port memory devices are used to facilitate simultaneous read and write operations, then processing time is reduced, but device size and cost increase significantly
Solution Approach 1:
The memory device is segmented into multiple banks (even banks and odd banks), where each bank operates independently. This segmentation allows simultaneous read and write operations to occur in different banks, effectively providing dual-port functionality while using standard single-port memory devices, thus avoiding the area and cost penalties of actual dual-port memory.
Solution Approach 2:
The patent transitions from a single-port time-sequential access model to a multi-bank parallel access model by adding a bank dimension. The controller manages access across multiple banks, allowing operations that would sequentially access the same memory location to instead access different banks simultaneously, achieving dual-port functionality without dual-port hardware.
2Loss of time
If dual port memory devices are used to facilitate simultaneous read and write operations, then processing time is reduced, but cost increases
Solution Approach 1:
The memory device is segmented into multiple banks (even banks and odd banks), where each bank operates independently. This segmentation allows simultaneous read and write operations to occur in different banks, effectively providing dual-port functionality while using standard single-port memory devices, thus avoiding the area and cost penalties of actual dual-port memory.
Solution Approach 2:
The patent uses multiple inexpensive single-port memory devices instead of one expensive dual-port memory device. By distributing the functionality across multiple cheaper components, the overall system cost is reduced while achieving the same performance benefit of simultaneous read and write operations.
3Loss of time
If clock speed is increased to meet processing demands, then processing time is reduced, but dynamic power consumption increases
Solution Approach 1:
The memory device is segmented into multiple banks (even banks and odd banks), where each bank operates independently. This segmentation allows simultaneous read and write operations to occur in different banks, effectively providing dual-port functionality while using standard single-port memory devices, thus avoiding the area and cost penalties of actual dual-port memory.
Solution Approach 2:
The patent enables continuous memory access operations by allowing read and write operations to proceed simultaneously in different banks. This eliminates the idle time that would occur in single-port memory where one operation must wait for the other to complete, maintaining continuous productive action without increasing clock speed and its associated power consumption.
4Productivity
If the number of processing engines is increased to meet processing demands, then throughput is improved, but logic size and routing complexity increase
Solution Approach 1:
The memory device is segmented into multiple banks (even banks and odd banks), where each bank operates independently. This segmentation allows simultaneous read and write operations to occur in different banks, effectively providing dual-port functionality while using standard single-port memory devices, thus avoiding the area and cost penalties of actual dual-port memory.
Data Source
Figure 1A
Figure 1B
Figure 2
AI summary
A method and apparatus single port memory devices to be accessed as pseudo two port memory devices. An access table is created to map the single port memory device to a single port even bank and a single port odd bank. The single port memory device is then accessed based on the mapping. An initial number of entries from the access table are retrieved in order to read addresses in the memory device until a predetermined delay expires. Simultaneous operations are then performed to read from rows in the memory device and write to rows in the memory device. Once all memory addresses have been read, write operations are sequentially performed in rows of the memory device based on the remaining entries of the acess table.