LDPC Memory Controller With Block-Shifted Partial Parallel Decoding
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Solution Overview
Problem
Existing LDPC decoding methods for long codes require many operation circuits for full parallel processing, making them impractical due to the high circuit scale needed.
Innovation Solution
A memory controller employing partial parallel processing using a check matrix composed of unit matrices, where each row of the unit matrix is sequentially shifted, allowing for efficient decoding with reduced circuit scale by performing operations in block units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If full parallel processing is used for LDPC coded data, then decoding speed is improved, but circuit scale increases significantly making it impractical
Solution Approach 1:
The patent divides the check matrix into multiple blocks, where each block corresponds to a sub-matrix. This segmentation allows the decoding process to be divided into multiple stages, with each stage processing one block at a time. The check matrix H is partitioned into blocks H1, H2, ..., Hm, and decoding proceeds by processing these blocks sequentially rather than all simultaneously, thus reducing the parallel circuit scale while maintaining reasonable decoding speed.
Solution Approach 2:
The patent employs a dynamic decoding approach where the processing block is shifted across the check matrix in multiple stages. Instead of static full parallel processing, the system dynamically moves through different blocks in sequence, with each stage processing a specific block while others remain inactive or in different processing states. This dynamic staging reduces the number of circuits needed at any given moment.
2Device complexity
If partial parallel processing in block units is used, then circuit scale is reduced, but decoding efficiency may be compromised
Solution Approach 1:
The patent ensures continuous useful action by overlapping the processing of different blocks across multiple stages. While one block is being processed in the current stage, other blocks are prepared for subsequent stages or have completed previous stages. This continuous pipeline approach ensures that the decoding process maintains high efficiency despite the reduced parallel circuit scale, as circuits are continuously utilized across different blocks rather than remaining idle.
Solution Approach 2:
The patent performs preliminary actions by pre-organizing the check matrix into blocks and pre-planning the multi-stage processing sequence. Before actual decoding begins, the system prepares the block structure and staging plan, allowing for efficient execution during the decoding process. This preliminary organization enables the reduced circuit scale to operate at high efficiency without ad-hoc reconfiguration during processing.
Data Source
AI summary
A memory controller including a buffer configured to perform decoding frame-unit data decoded by an LDPC decoder through partial parallel processing based on a check matrix made up of a block of a unit matrix and a plurality of blocks in which each row of the unit matrix is sequentially shifted and store threshold decision information of the data read from a memory section, an LLR conversion section configured to convert the threshold decision information to an LLR, an LMEM configured to store probability information β calculated during iteration processing that repeatedly performs column processing and row processing based on the LLR in an iteration unit equal to or smaller than a size of the block, and a CPU core configured to transfer the probability information β stored in the LMEM to the buffer every time the iteration processing in the iteration unit is completed.