Layered LDPC Decoder Memory Layout for Parallel Circulant Processing
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Solution Overview
Problem
Multi-level low-density parity-check code decoders face high hardware complexity and power consumption, limiting their practical implementation.
Innovation Solution
A memory architecture that connects memory modules directly to mapping elements, allowing for the simultaneous processing of multiple circulants, reducing complexity and power consumption by optimizing the decoder's architecture.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-level low-density parity-check code decoders are designed to process multiple circulants simultaneously, then decoding performance and throughput are improved, but hardware complexity and power consumption increase significantly
Solution Approach 1:
The decoder architecture is segmented into multiple processing layers, where each layer handles a subset of circulants. This segmentation allows parallel processing of multiple circulants while distributing hardware complexity across manageable layers, preventing any single processing unit from becoming overly complex
Solution Approach 2:
The patent introduces a layered dimension to the decoder architecture, organizing circulant processing in multiple hierarchical layers rather than a single flat structure. This dimensional organization enables simultaneous processing of multiple circulants while managing hardware complexity through structured layering
2Productivity
If memory modules are connected directly to mapping elements in a layered architecture, then routing congestion and memory collision are reduced, but memory architecture complexity increases
Solution Approach 1:
The memory architecture is segmented into multiple memory modules, each directly connected to specific mapping elements in the layered structure. This segmentation eliminates routing congestion by providing dedicated memory access paths for each layer, preventing memory collisions while maintaining organized complexity
Solution Approach 2:
The memory modules are designed with universal interfaces that can serve multiple mapping elements across different layers. This multi-functionality allows the same memory module design to be reused throughout the architecture, reducing overall complexity despite the expanded memory system
Data Source
AI summary
A hard decision memory interacts with a multi-layered low-density parity-check decoder by sending multiple L values and E values to a multi-layered low-density parity-check decoder (LDPC), and the L value E value hard decision memory (LE hard decision memory) receives one or more hard decisions. The LE hard decision memory comprises a global mapping element to interleave L values from a first and second circulant and store the interleaved values in a first memory element. A low-density parity-check decoder then processes the circulants from the first memory element and stores output in a second memory element. The LE hard decision memory does not include any mux-demux elements. The use of the LE hard decision memory results improved multi-level LDPC decoding of an LDPC encoded message.