LDPC Decoder Input Memory Loading With Interlaced LLR Streams
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Solution Overview
Problem
The existing LDPC decoder systems face inefficiencies in loading data into the input memory, particularly in reducing the number of writes required for LDPC frames, which can lead to increased silicon surface area and power consumption, especially when handling interlaced LLRs.
Innovation Solution
The implementation of a serial/parallel conversion module and a row/column interlacing device with a two-dimensional FIFO ring buffer allows for reduced memory accesses by interlacing information and parity LLRs, enabling efficient loading of LDPC frames with fewer write operations and integrating deinterlacing functions within the decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is loaded sequentially into input memory, then memory access is simple, but the number of write operations increases and productivity decreases
Solution Approach 1:
The input memory is divided into multiple banks (first memory bank, second memory bank, etc.), allowing parallel write operations to different banks simultaneously. This segmentation enables the system to load multiple LLRs in parallel, reducing the total number of write operations while maintaining manageable access complexity through organized bank structure.
Solution Approach 2:
The patent introduces a two-dimensional FIFO ring buffer structure that organizes data in both row and column dimensions. This two-dimensional organization allows the system to perform row-wise or column-wise reads depending on the operation mode, adding a dimensional aspect to memory access that enables parallel processing and reduces write operations without overly complicating the access mechanism.
2Adaptability or versatility
If dedicated deinterlacing device is added, then deinterlacing function is complete, but silicon surface area increases
Solution Approach 1:
The two-dimensional FIFO ring buffer is designed to serve multiple functions: it acts as both a buffering structure for LLR data and a deinterlacing device. By organizing data in two dimensions and enabling row/column access modes, the same structure performs both data buffering and deinterlacing operations, eliminating the need for a separate dedicated deinterlacing device and thus saving silicon surface area.
Solution Approach 2:
The patent merges the deinterlacing function with the existing FIFO buffer structure. Instead of adding a separate deinterlacing device, the system combines these functions by enabling the FIFO buffer to operate in different modes (row-wise or column-wise access) to achieve both buffering and deinterlacing, thereby reducing overall device complexity and silicon area.
3Reliability
If more write operations are performed, then data loading is thorough, but power consumption increases
Solution Approach 1:
By segmenting the input memory into multiple banks, the system can perform parallel write operations to different banks simultaneously. This reduces the total number of sequential write operations required to load the same amount of data, thereby maintaining complete data loading while reducing the cumulative power consumption associated with each write operation.
Solution Approach 2:
The two-dimensional FIFO ring buffer pre-organizes data in row and column structures before writing to memory banks. This preliminary organization allows the system to load data more efficiently in parallel operations, reducing the total number of write operations required and consequently lowering power consumption while ensuring complete and thorough data loading.
Data Source
AI summary
An input memory of an LDPC decoder is loaded with data corresponding to an LDPC frame to be decoded and including N LLRs, of which K are information LLRs and N−K are parity LLRs. At least one stream is formed of binary words of a first type, each corresponding to multiple information LLRS, with the aid of a serial/parallel conversion module, and at least one stream is formed of binary words of a second type, each corresponding to multiple parity LLRs, with the aid of a row/column interlacing device comprising a two-dimensional first-in first-out ring buffer. The first memory accesses are made in page mode in order to write the binary words of the first type to a first zone of the input memory, and the second memory accesses are made in page mode in order to write the binary words of the second type to a second zone.