LDPC Memory Decoding with Majority Logic Error Preprocessing
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Solution Overview
Problem
As memory devices are scaled and the number of bits stored per cell increases, the error rate in computing devices such as floating gate memory and Phase Change Memory (PCM) rises due to sources like random noise, cell-to-cell interference, and charge leakage, necessitating improved error correction algorithms.
Innovation Solution
The implementation of a Low-Density Parity Code (LDPC) algorithm with a preprocessing majority logic decode stage, utilizing a parity check matrix to correct errors by majority logic decoding and further decoding with Bit-Flipping Decode (BFD) or Min-Sum algorithms, depending on error severity, without incurring additional encoding processes or data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are scaled and bits per cell are increased, then storage capacity is improved, but error rate increases
Solution Approach 1:
The patent applies preliminary action by performing majority logic decoding as a preprocessing step before the main ECC decoding. This preliminary stage identifies and corrects certain error patterns early, preparing the data for more sophisticated decoding algorithms and improving overall error correction effectiveness in scaled memory devices
Solution Approach 2:
The patent changes the parameter of decoding complexity by implementing a hierarchical decoding approach that starts with simple majority logic and progresses to more complex algorithms like Min-Sum and Bit-Flipping Decode only when necessary. This parameter change allows effective error correction without always incurring the full computational cost of advanced algorithms
2Reliability
If Min-Sum algorithms are invoked to correct errors, then error correction performance is improved, but decoding latency increases
Solution Approach 1:
The patent segments the decoding process into multiple stages: a first stage using majority logic decode for quick corrections, and a second stage using more intensive algorithms like Min-Sum only when needed. This segmentation allows the system to achieve high error correction performance for most codewords (approximately 99%) while avoiding the latency penalty of invoking Min-Sum algorithms in every case
Solution Approach 2:
The patent applies partial action by using the computationally intensive Min-Sum algorithms only partially - specifically, only when the initial majority logic decoding fails to correct errors. For the majority of codewords where errors are fewer or more correctable, the simpler majority logic suffices, avoiding unnecessary computational overhead and latency
3Reliability
If additional encoding processes or data are added to improve error correction, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies universality by designing a decoding architecture that handles multiple error correction scenarios through a unified hierarchical approach. The same parity check matrix and decoding framework accommodate both simple correctable errors (handled by majority logic) and more complex error patterns (requiring Min-Sum or Bit-Flipping), eliminating the need for separate encoding schemes for different error types
Data Source
AI summary
Technology for correcting memory read errors including a preprocessing majority logic decode based on a plurality of identity structures of a parity check matrix, before ECC decoding using the parity check matrix, to estimate a set of erased or punctured bits of a codeword.