Layered LDPC Decoder Memory Scheduling for Fewer Patch LLRs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing decoding hardware for low-density parity-check (LDPC) codes faces challenges in minimizing memory requirements and optimizing processing schedules to reduce pipeline conflicts and memory capacity needs.
Innovation Solution
The proposed solution involves a decoder architecture with an LLR memory structure that uses double buffering and an optimized processing schedule for the parity check matrix (PCM) to minimize the number of patch LLRs that need to be stored, thereby reducing memory requirements and pipeline conflicts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a layered decoding schedule is used to process the parity check matrix in parts, then faster convergence is achieved, but pipeline conflicts occur that reduce throughput
Solution Approach 1:
The patent identifies pipeline conflicts in advance by analyzing the parity check matrix structure and preprocessing schedule. This allows the system to prepare patch LLR values before they are needed, storing them in a separate buffer memory block. By performing this preliminary identification and preparation, the system avoids stalls during the actual decoding process, maintaining both fast convergence and high throughput.
2Productivity
If pipeline stages are increased to provide high operating frequency, then throughput is improved, but data hazards cause stall cycles that reduce efficiency
Solution Approach 1:
The patent introduces a separate buffer memory block as an intermediary between the main LLR memory and the decoding logic. This intermediary stores patch LLR values that need to be applied after pipeline stages complete, allowing the pipeline to continue operating at high frequency without waiting for data hazards to resolve. The intermediary buffer decouples the high-speed pipeline operation from the data dependency constraints, maintaining both throughput and accuracy.
3Quantity of substance
If the number of patch LLRs stored in LLR memory is reduced, then memory requirements are minimized, but pipeline conflicts cannot be fully resolved
Solution Approach 1:
The patent segments the LLR storage into two distinct parts: the main LLR memory that stores current and previous codeword LLRs, and a separate buffer memory block that stores only the patch LLRs needed for pipeline conflict resolution. This segmentation allows the system to minimize the total memory capacity by storing only essential patch values in the buffer, while maintaining high throughput by having immediate access to these critical values without relying on large memory capacity.
Data Source
Figure 1
Figure 2
Figure 3
AI summary
The disclosure generally relates to improvements of a log-likelihood ratios (LLRs) memory structure and memory capacity of a decoding hardware (also referred to as a decoder) in decoding a sequence of codewords encoded with a low-density parity-check (LDPC) code (e.g. a quasi-cyclic (QC) LDPC code). Further, the disclosure relates to the optimization of a processing schedule of a parity check matrix (PCM) describing the LDPC code so as to reduce or minimize the number of patch LLRs that need to be (simultaneously) stored in an LLR memory of a decoder.