LDPC Decoder Memory Permutation for NAND Flash Error Correction

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Solution Overview

Problem

The reliability of memory devices is compromised due to fine processing and the use of multi-level cells, leading to increased error rates, which existing error correction codes struggle to address effectively, particularly in NAND flash memory devices.

Innovation Solution

A low-density parity check (LDPC) decoder is implemented with a variable node processing unit and a check node processing unit, featuring interconnected memory elements that undergo cyclic permutations to support various H matrices, enabling efficient error correction through hard and soft decision decoding processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If existing error correction codes are used, then the memory device can store data, but the reliability is degraded due to fine process and multi-level cells causing increased error rates

Engineering Contradiction:

Improvedata reliabilityVSAvoiderror rate

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent employs LDPC decoding algorithms with configurable H matrices that can be adjusted based on channel conditions and error patterns. The decoder supports multiple H matrices with different densities and structures, allowing dynamic parameter changes to optimize error correction performance for different memory device characteristics and error rates

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The LDPC decoder is designed to handle multiple types of error correction scenarios using a unified architecture. It can process both systematic and non-systematic codes, support different code rates, and adapt to various memory device types (NAND flash, PCM, etc.), making it a universal error correction solution that improves reliability across different devices

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Reliability

If LDPC decoder is implemented with multiple H matrices, then error correction capability is enhanced, but device complexity increases

Engineering Contradiction:

Improveerror correction capabilityVSAvoiddecoder complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The LDPC decoder architecture is segmented into distinct functional units: H matrix storage units, syndrome calculation units, and decoding processing units. Each H matrix is stored in separate memory structures, and the decoding process is divided into systematic and non-systematic processing paths, reducing the complexity of managing multiple H matrices simultaneously

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The decoder dynamically selects and switches between different H matrices based on the specific error patterns detected and the code type being decoded. The H matrix selection is performed on-the-fly without requiring complete reconfiguration of the decoder architecture, allowing adaptive complexity management while maintaining high error correction capability

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS10374630B2Low-density parity check decoder, a storage device including the same, and a method

Publication Date: 2019.08.06 SAMSUNG ELECTRONICS CO LTD

AI summary

A low-density parity check (LDPC) decoder may include a variable node processing unit and a check node processing unit. The check node processing unit includes memory elements storing a check node value. The memory elements are interconnected through two or more paths, and each of the paths may include a total or partial cyclic permutation of the memory elements to transmit the check node value.