LDPC Decoding for Faster and More Accurate Memory Reads
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing data reading methods from semiconductor memory devices face challenges in accurately correcting errors during the reading process, leading to inefficiencies in resource utilization and increased stress on storage devices due to the need for additional reads when hard decisions fail.
Innovation Solution
A method involving a two-step low-density parity check (LDPC) decoding process, where data is initially read using normal voltages, followed by a hard decision and subsequent soft decision using fractional read voltages, to generate reliability bits and perform error correction, reducing the need for additional reads by improving the accuracy of hard decisions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hard decision reading is performed using normal read voltages, then reading speed is improved, but error correction accuracy deteriorates
Solution Approach 1:
The patent segments the error correction process into two distinct phases: hard decision decoding using normal read voltages for speed, and soft decision decoding using fractional read voltages for accuracy. This segmentation allows the system to leverage the speed advantage of hard decisions while mitigating their accuracy limitations through selective soft decision intervention.
Solution Approach 2:
The patent changes the read voltage parameter from normal voltages to fractional read voltages when soft decision decoding is required. By adjusting the voltage parameter, the system can extract more reliable signal information from memory cells, thereby improving error correction accuracy without permanently sacrificing reading speed.
2Reliability
If soft decision reading is performed to improve error correction, then error correction accuracy is improved, but resource consumption increases
Solution Approach 1:
The patent applies partial soft decision action by performing soft decision decoding only on specific data blocks that require it, rather than universally applying soft decision to all reads. The controller determines which blocks need soft decision based on hard decision results, applying the more resource-intensive method only where necessary.
Solution Approach 2:
The patent implements a feedback mechanism where the controller monitors hard decision decoding results and uses this information to determine whether soft decision decoding is needed. This feedback loop allows the system to dynamically adjust its error correction strategy, consuming additional resources only when the initial hard decision fails to achieve sufficient reliability.
3Reliability
If additional reads are performed to correct errors, then error correction capability is improved, but device stress increases
Solution Approach 1:
The patent performs preliminary hard decision decoding using normal read voltages before resorting to additional soft decision reads. This preliminary action allows the system to correct many errors without requiring additional reads, thereby reducing device stress. Soft decision decoding with fractional voltages is prepared as a backup strategy only when needed.
Solution Approach 2:
The patent changes the read voltage parameter to fractional voltages for soft decision decoding, which allows extraction of more information from the same memory cells without requiring additional physical reads. This parameter change enables improved error correction capability while minimizing additional device stress compared to performing multiple normal reads.
Data Source
AI summary
Methods of reading data from storage devices may include reading data stored in the storage device using normal read voltages; performing a first low density parity check (LDPC) decoding based on the read data; generating reliability bits of each of read bits according to the decoding result, the read bits being bits of the read data; and performing a second low density parity check (LDPC) decoding based on the read data and the reliability bits to perform a first error correction on the read data.