LDPC Decoder Memory Layout for Parallel Node Processing
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Solution Overview
Problem
Existing LDPC decoders face challenges in achieving a high decoding rate while minimizing hardware complexity, particularly in mobile communication systems, due to the need for a trade-off between parallel structure implementation and memory control complexity.
Innovation Solution
A decoding apparatus and method that employs a memory structure where variable node processors read and write data in a column direction, and check node processors read and write in a row direction, with a memory access control module generating signals for efficient storage and retrieval of hard decision bits and soft metric values, allowing for parallel processing and reduced hardware complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a parallel structure decoder is implemented to improve decoding rate, then productivity is improved, but device complexity increases due to memory control requirements
Solution Approach 1:
The memory module is divided into multiple unit memories (first unit memory, second unit memory, third unit memory, fourth unit memory) that are selectively accessed by different node processors. This segmentation allows parallel processing while simplifying the control logic for each processor, as each processor only needs to manage access to specific memory units rather than controlling the entire memory space.
Solution Approach 2:
The same memory module serves multiple functions: storing hard decision bits, storing soft metric values, and supporting both variable node processors and check node processors. The memory system is designed to handle different data types and access patterns through selective enabling, reducing the need for separate dedicated memory structures for each function.
2Productivity
If more node processors are added to increase parallel processing capability, then productivity is improved, but device complexity increases due to additional memory access control requirements
Solution Approach 1:
Multiple node processors (first, second, third, fourth variable node processors and check node processors) share a common memory module rather than each having dedicated memory. The memory access control module manages all processor accesses through selective enabling of unit memories, merging memory resources to reduce overall hardware complexity while maintaining parallel processing capability.
Solution Approach 2:
The memory access control module dynamically enables or disables specific unit memories based on which node processor is currently active and what operation is being performed. This dynamic control allows the system to support multiple processors without requiring permanent dedicated memory allocations for each, reducing hardware complexity while maintaining flexibility for parallel operations.
Data Source
AI summary
An apparatus and method for decoding low density parity check (LDPC) codes are provided. A memory module configured by a plurality of unit memories stores a reliability value. Variable node processors perform a computation associated with a variable node, and update data of the memory module in a column direction, respectively. Check node processors perform a computation associated with a check node, and update data of the memory module in a row direction, respectively. A parity checker determines if all errors have been corrected such that an iterative decoding process is performed. A memory access control module selects a unit memory to be updated by a variable node processor or a check node processor.