LDPC Decoder Memory Shuffling for Low-Latency Soft-Decision Updates
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Solution Overview
Problem
Existing LDPC decoders face inefficiencies in processing large and sparse parity check matrices, leading to increased storage requirements and latency issues due to the need to access and store data from multiple memory locations, which affects the correct ordering and timing of updates in the decoding process.
Innovation Solution
A configurable LDPC decoder architecture that utilizes multiple independently addressable memories and check node processing systems to generate and update soft decision data, with a shuffling system that ensures data is accessed and reordered efficiently, allowing for wider memory access and reduced latency by discarding unnecessary data and using gap-closing hardware to adapt to different sub-matrix sizes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is accessed from multiple memory locations to process large and sparse parity check matrices, then decoding capability is improved, but storage requirements and access complexity increase
Solution Approach 1:
The parity check matrix is divided into sub-matrices, and the decoding process is segmented into processing different sub-matrices sequentially. This allows the decoder to handle large matrices by breaking them into manageable chunks, reducing the complexity of storing and accessing the entire matrix at once while maintaining full decoding capability.
Solution Approach 2:
The shuffling system pre-arranges data in memory locations before processing begins, and gap-closing hardware pre-prepares replacement values for discarded data. This preliminary organization eliminates the need for complex real-time data retrieval from multiple locations during decoding, reducing access complexity while preserving decoding functionality.
2Reliability
If data is accessed from multiple memory locations, then complete parity check processing is improved, but latency increases due to access and ordering requirements
Solution Approach 1:
The shuffling system organizes data in optimal memory locations before processing starts, and gap-closing hardware prepares replacement values in advance. This preliminary arrangement eliminates latency-causing data retrieval operations during the actual decoding process, ensuring complete parity check processing without time penalties.
Solution Approach 2:
The system discards certain data elements that would require complex retrieval and ordering operations, using gap-closing hardware to fill in the missing values with pre-computed replacements. This skipping of problematic data access patterns reduces latency while maintaining processing completeness through alternative value generation.
3Productivity
If wider memory access is implemented to reduce latency, then decoding speed is improved, but storage requirements increase
Solution Approach 1:
Instead of implementing one large wide memory that would require excessive storage capacity, the system segments memory access into multiple narrower memory locations that are accessed in a coordinated sequence by the shuffling system. This achieves effective wide access performance through parallel or sequential access to multiple narrower units, maintaining decoding speed without the storage overhead of a single large memory.
Data Source
AI summary
Methods and apparatus for decoding LDPC code provide that an LDPC code may be represented as a Tanner graph comprising bit nodes and check nodes and connections between them. A configurable LDPC decoder supporting many different LDPC codes having any sub-matrix size includes several independently addressable memories which are used to store soft decision data for each bit node. The decoder further includes a number P of check node processing systems which generate updated soft decision data. The updated values are then passed back to the memories via a shuffling system. If the number of check nodes processed in parallel by the check node processing systems is PCNB (where P≥PCNB) and the soft decision data for a bit node is of word size q bits, the total width of the independently addressable memories is larger than PCNB*q bits.