LDPC Code Structure for MIMO-OFDM Layered Decoding
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Solution Overview
Problem
Existing Low Density Parity Check (LDPC) codes for MIMO OFDM communications face challenges in achieving excellent error rate performance with modest computational and memory requirements, particularly in wireless LANs, due to inefficiencies in hardware implementation and variability in code performance across similar codeword sizes and code rates.
Innovation Solution
The implementation of LDPC codes with a sparse arrangement of cyclically shifted permutation matrices, allowing for column and row reordering in a macro matrix, which enhances error rate performance and maintains computational efficiency, enabling layered decoding and high parallelism.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDPC codes are used for MIMO OFDM communications, then error correction capability is provided, but bit error rate performance is insufficient and computational requirements are high
Solution Approach 1:
The patent applies parameter changes by systematically varying key code parameters including block length (e.g., 192, 384, 768, 1536 bits), code rate (e.g., 1/2, 2/3, 3/4), and permutation matrix sizes (e.g., 4x4, 8x8, 16x16) to optimize performance for different MIMO configurations and channel conditions while maintaining manageable computational complexity
Solution Approach 2:
The patent segments the LDPC code structure into multiple blocks, where each block contains information bits and parity bits separated by punctured bits. The code is organized with systematic structure where information bits are followed by parity bits, allowing independent processing of different code blocks and reducing overall computational burden
2Reliability
If LDPC codes with longer codeword lengths are used to improve error rate performance, then reliability increases, but memory requirements and decoding complexity increase
Solution Approach 1:
The patent implements dynamic code configuration where the block length, code rate, and number of permutation matrices are adjustable based on channel conditions and performance requirements. This allows the system to adaptively select appropriate code parameters, using shorter codes when memory is constrained and longer codes when maximum reliability is needed
Solution Approach 2:
The patent provides a family of LDPC codes with varying parameters including block lengths of 192, 384, 768, and 1536 bits, allowing the system to select the appropriate code length based on the specific application requirements and available memory resources
3Productivity
If high-rate LDPC codes are used to increase data transmission efficiency, then productivity improves, but error correction capability deteriorates
Solution Approach 1:
The patent provides a comprehensive set of code rates including 1/2, 2/3, 3/4, and higher rates, allowing the system to select the appropriate code rate based on the desired balance between data transmission efficiency and error correction capability for different channel conditions
4Reliability
If complex LDPC code structures are used to improve error rate performance, then reliability increases, but ease of manufacture and implementation decreases
Solution Approach 1:
The patent provides a systematic family of codes with parameters that can be adjusted in discrete steps (block lengths of 192, 384, 768, 1536 bits; code rates of 1/2, 2/3, 3/4; permutation matrix sizes of 4x4, 8x8, 16x16), making it easier to implement and select appropriate codes for different applications without requiring complex custom designs
Data Source
AI summary
Transceiver circuitry for use in a multiple-input, multiple-output (MIMO), orthogonal frequency-division multiplexing (OFDM), communications environment, is disclosed. Error correction coding according to a fixed-block size code, such as low density parity check (LDPC) coding, is implemented. A specific LDPC code with excellent error rate performance is disclosed.