LDPC Decoder Min-Value Selection With Reduced Comparator Complexity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing LDPC decoders using the min-sum algorithm require complex circuitry to identify the two minimum values, leading to high hardware complexity, latency, and power dissipation, which is challenging for long codeword lengths.
Innovation Solution
The method approximates the problem of finding the two minimum values by identifying a first value as the minimum and a second value as the minimum among a subset, reducing the complexity of comparisons and circuitry required, while maintaining acceptable coding gain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the min-sum algorithm is used to identify the two minimum values in LDPC decoding, then decoding accuracy is improved, but hardware complexity increases
Solution Approach 1:
The patent segments the set of input values into multiple subsets and processes each subset separately to identify minimum values. Instead of comparing all values globally, the method divides the comparison task into smaller segments, reducing the complexity of identifying the two minimum values while maintaining decoding accuracy through the min-sum algorithm framework.
2Measurement precision
If complex circuitry is used to identify the two minimum values, then decoding precision is improved, but latency increases
Solution Approach 1:
By segmenting the value set into subsets and processing them in parallel or sequential stages, the patent reduces the critical path delay compared to a full-comparison approach. The segmentation allows for simpler comparison circuits at each stage, reducing overall latency while achieving the same decoding precision through the min-sum algorithm.
3Reliability
If complex circuitry is used to identify the two minimum values, then decoding accuracy is improved, but power dissipation increases
Solution Approach 1:
The segmentation approach reduces the number of simultaneous comparisons required, thereby reducing the active transistor count and dynamic power consumption. By dividing the value set into subsets, the circuit activates fewer components at any given time, lowering power dissipation while maintaining decoding accuracy through the structured min-sum algorithm implementation.
4Device complexity
If the number of comparators and multiplexers is reduced, then hardware complexity is reduced, but decoding performance degrades
Solution Approach 1:
The patent strategically segments the value processing into subsets, allowing the use of fewer comparators and multiplexers per stage while maintaining overall decoding performance. The segmentation enables a trade-off where reduced component count per segment is compensated by the structured approach of the min-sum algorithm, preserving coding gain with simplified hardware.
Solution Approach 2:
The method applies partial action by identifying minimum values from subsets rather than performing exhaustive comparisons across all values. This partial comparison approach reduces hardware requirements while the min-sum algorithm framework ensures that the decoding performance remains satisfactory, achieving an optimal balance between complexity and performance.
Data Source
Figure 1
Figure 2~3
Figure 4~5
AI summary
The present invention is directed toward identifying selected values from among a set of values. In accordance with an embodiment, a method of identifying two selected values from among a plurality of values comprises: partitioning the plurality of values into pairs of values; for each pair of values, using a comparator to select one of the two values to form a vector from the selected value of each pair; and applying the vector to a hardware unit that identifies first and second extreme values from among the values of the vector. Application areas are hardware LDPC decoders using an approximation of the sum-product algorithm such as the min-sum algorithm and its variations (e.g. normalized min-sum, offset min-sum, corrected min-sum, etc.).