LDPC Variable Node Adjustment for Higher NAND Error Tolerance
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Solution Overview
Problem
Existing memory systems face challenges in efficiently managing variable node data during data validation, particularly in solid-state drives, leading to high raw bit error rates (RBER) that affect the endurance and yield of NAND chips.
Innovation Solution
Implementing a min-sum decoder with adjustment factors (s = -1 or 1) for variable node data based on conditions such as bit flipping, check node status, and intrinsic likelihood, enhancing the RBER tolerance by adjusting variable node messages in LDPC codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If min-sum decoder is used for LDPC code decoding, then hardware implementation cost is reduced and speed is improved, but tolerated raw bit error rate (RBER) is insufficient
Solution Approach 1:
The patent modifies the variable node data by applying an adjustment factor (multiplying by -1 or 1) based on specific conditions including bit flipping status, check node bad status, and intrinsic likelihood. This parameter change enhances the tolerated RBER while maintaining the efficient min-sum decoding approach, resolving the contradiction between decoding performance and error tolerance
Solution Approach 2:
The patent implements a feedback mechanism where the adjustment factor application depends on the intrinsic likelihood of the variable node and the status of connected check nodes. This feedback loop allows the decoder to adaptively adjust variable node data based on decoding progress and error patterns, improving RBER tolerance without sacrificing decoding speed
2Ease of manufacture
If PLC NAND chips are used, then manufacturing cost is reduced, but RBER is higher compared to QLC or TLC NAND chips
Solution Approach 1:
The patent converts the inherent high RBER characteristic of PLC NAND chips into a manageable parameter by applying adjustment factors to variable node data. This approach transforms the harmful high error rate into an opportunity to demonstrate enhanced correction capability, allowing PLC chips to achieve acceptable reliability while maintaining manufacturing cost advantages
3Reliability
If adjustment factor is applied to variable node data, then tolerated RBER is enhanced, but decoding complexity increases
Solution Approach 1:
The patent applies the adjustment factor selectively to specific variable nodes based on local conditions such as intrinsic likelihood thresholds and connected check node status. This localized approach enhances RBER tolerance only where needed, avoiding unnecessary complexity in the overall decoding process while maintaining efficiency in regions where adjustment is not required
Data Source
AI summary
This application is directed to data validation in an electronic device. The electronic device identifies a set of check nodes associated with a variable node that corresponds to a first data bit in a block of data, and obtains check node data from each check node. A hard decision likelihood is determined based on a check node data set including the check node data of each of the set of check nodes. The electronic device dynamically determines an adjustment factor based on the hard decision likelihood. Variable node data is determined for each of the set of check nodes based on the adjustment factor. In some embodiments, each check node is configured to verify validity of a set of data bits including the first data bit, and the check node data of each of the set of check nodes indicates a likelihood of the set of data bits being erroneous.