LDPC Decoder Node Locking for Low-Power Iterative Decoding

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Solution Overview

Problem

Conventional low density parity check (LDPC) decoding systems are overly power hungry, consuming excessive energy during the decoding process.

Innovation Solution

The implementation of a low-power LDPC decoding method that dynamically locks variable and check nodes based on probability thresholds and iteration counts, reducing unnecessary calculations and message passing, thereby conserving energy by minimizing operations for nodes that have already converged or are unlikely to change during subsequent iterations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If conventional LDPC decoding is performed with all variable nodes and check nodes actively participating in message passing, then decoding accuracy is maintained, but power consumption becomes excessive

Engineering Contradiction:
Improvepower consumptionVSAvoiddecoding accuracy
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent segments the LDPC decoder into active and inactive variable nodes and check nodes. During decoding iterations, nodes that have converged (met their target probability thresholds) are segmented into an inactive state, while nodes that have not yet converged remain active. This segmentation allows the decoder to maintain accuracy for nodes that need processing while eliminating unnecessary computations for nodes that have already converged, thereby reducing power consumption without sacrificing decoding accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies partial action by performing message passing operations only on the subset of nodes that require further processing. Instead of executing full decoding operations on all nodes in each iteration, the system performs partial operations only on active nodes that have not yet met their convergence criteria. This partial action approach maintains decoding accuracy for nodes that need it while avoiding excessive computations on nodes that have already converged, thus resolving the contradiction between power consumption and decoding accuracy.

Inventive Principle:
Principle #16Partial or excessive action

2Productivity

If message passing is performed for all iterations and all nodes, then complete decoding is achieved, but unnecessary energy expenditure occurs on settled nodes

Engineering Contradiction:
Improvedecoding efficiencyVSAvoidenergy expenditure
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent introduces dynamic node states that change during the decoding process. Each variable node and check node transitions between active and inactive states based on their convergence status. This dynamic approach allows the system to adapt the decoding process in real-time, activating or deactivating nodes as needed. By making the decoding process dynamic rather than static, the system improves decoding efficiency by focusing resources on nodes that need processing while reducing energy expenditure on nodes that have already converged.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements self-service through automatic node state management. Each node monitors its own convergence status and automatically transitions to an inactive state when it meets its target probability threshold, without requiring external control. This self-service mechanism allows the decoding system to automatically optimize its own resource allocation, improving decoding efficiency by eliminating unnecessary operations while maintaining energy efficiency by stopping computations for converged nodes.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10069514B2Low-power low density parity check decoding
Publication Date: 2018.09.04 MAXLINEAR INC
  • US10069514B2 patent drawing
  • US10069514B2 patent drawing
  • US10069514B2 patent drawing

AI summary

Methods and systems are provided for low-power decoding. An example system may include one or more storage circuits and a decoder circuit. The decoder circuit may implement a plurality of nodes for use during decoding, including at least one data generating node and at least one data checking node, and the storage circuits may store status information associated with the nodes, the status information indicating when each corresponding node is locked or unlocked. During decoding operations, the decoder circuit may set the status information to lock one or more of the nodes based on one or more locking conditions, and may cease decoding based on one or more ceasing conditions. The decoder circuit may locks a data generating node when a corresponding calculated value meets a particular condition, and may lock a data checking node when all data generating nodes associated with it are locked.