LDPC Decoder Node Memory Layout for Higher Throughput
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Solution Overview
Problem
Conventional LDPC decoders face challenges in achieving high throughput while maintaining low complexity, particularly due to the need for separate memory for storing V2C and C2V messages, which increases hardware complexity and reduces decoder efficiency.
Innovation Solution
The proposed LDPC decoding apparatus employs a node memory-based approach, utilizing a single node processor and edge memory to store and process messages, eliminating the need for separate C2V and V2C message memories, and implementing a variable node-based serial scheduling scheme to enhance throughput and reduce memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If separate memory is used for storing V2C and C2V messages, then message storage capability is improved, but hardware complexity increases
Solution Approach 1:
The patent merges the separate V2C message memory and C2V message memory into a single node memory structure. The node memory stores both types of messages by utilizing different memory addresses or regions, thereby reducing the total number of memory components and simplifying the overall hardware architecture while maintaining the capability to store both V2C and C2V messages
Solution Approach 2:
The node memory is designed as a universal memory structure that can serve multiple functions: storing V2C messages, storing C2V messages, and supporting the variable node-based serial scheduling scheme. This multi-functional design eliminates the need for dedicated separate memories for each message type, reducing hardware complexity
2Ease of manufacture
If separate memory is used for storing V2C and C2V messages, then message organization is improved, but decoder efficiency decreases
Solution Approach 1:
The patent implements a dynamic memory access scheme where the node processor can flexibly access and update messages in the node memory based on the current processing needs. The variable node-based serial scheduling scheme dynamically determines which messages to read and write in each iteration, optimizing the decoding process efficiency while maintaining proper message organization through controlled access patterns
Solution Approach 2:
While using a single node memory, the patent segments the memory into different logical regions or address spaces for V2C and C2V messages. This segmentation maintains the organizational benefits of separate memories while avoiding the hardware complexity of physically separate memory components, thereby preserving decoder efficiency
3Productivity
If multiple processors are used, then decoding throughput is improved, but hardware complexity increases
Solution Approach 1:
The patent implements a variable node-based serial scheduling scheme that enables continuous processing of decoding operations through systematic iteration. The single node processor continuously updates messages and progresses through the decoding iterations without idle time, achieving high decoding throughput by maximizing the utilization of the single processor rather than requiring multiple processors
Solution Approach 2:
The decoding process uses periodic iteration cycles where the node processor systematically updates V2C messages, then C2V messages, then V2C messages again in a repeating pattern. This periodic action structure allows a single processor to achieve high throughput through efficient cycling through the decoding steps without requiring multiple concurrent processors
Data Source
AI summary
An apparatus is provided for decoding a Low-Density Parity Check (LDPC) code in a communication system. In the LDPC decoding apparatus, an edge memory stores a message delivered through an edge between a variable node and a check node. A node memory stores a node value. A node processor performs a node processing operation using information stored in at least one of the node memory and the edge memory, stores a check node value generated by performing the node processing operation in the node memory, and stores a message generated by performing the node processing operation in the edge memory. A switch switches outputs of the node memory and the node processor through a permutation operation. A parity check verifier parity-checks an output from the node memory. A controller provides a control signal for controlling the node processor.