LDPC Variable Node Updates for Multi-Level Memory Error Correction
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Solution Overview
Problem
Semiconductor memory devices face challenges in data protection due to random bit errors caused by alpha particles and on-chip/off-chip noise sources, leading to increased data errors and susceptibility to soft errors, especially as process geometries shrink and memory cells store multiple data bits, complicating error correction in non-binary LDPC codes.
Innovation Solution
Implementing symbol-based variable node updates for binary LDPC codes by grouping variable nodes into multi-variable nodes that account for symbol likelihoods, enhancing decoding performance and reducing computational complexity at check nodes through iterative message passing algorithms in Tanner graphs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-binary LDPC codes are used to handle multi-level memory cell values, then error correction capability is improved, but computational complexity at check nodes increases significantly
Solution Approach 1:
The patent combines multiple variable nodes into a single multi-variable node that represents a symbol (multiple bits) from a non-binary LDPC code. This merging allows the variable node to directly process symbol likelihoods from multi-level memory cells, maintaining simplicity while improving error correction capability for non-binary codes
Solution Approach 2:
Instead of applying complex non-binary operations at check nodes, the patent inverts the approach by maintaining binary LDPC code structures at check nodes while handling non-binary symbol information at variable nodes. This inversion preserves check node simplicity while still enabling error correction for multi-level memory cells through symbol-based variable node updates
2Device complexity
If binary LDPC codes are used to maintain simplicity at variable nodes, then decoding complexity is reduced, but error correction capability for multi-level memory cell values is insufficient
Solution Approach 1:
The patent merges multiple binary variable nodes into a single multi-variable node that represents a symbol containing multiple bits. This multi-variable node processes symbol likelihoods from multi-level memory cells, enabling binary LDPC codes to handle non-binary data while maintaining decoding simplicity at check nodes
Solution Approach 2:
The patent introduces symbol likelihoods as an intermediary representation that bridges binary LDPC codes and multi-level memory cell values. The symbol likelihoods carry information about multi-level cell states through the binary LDPC decoding process, enabling error correction for multi-level cells while maintaining binary code simplicity
Data Source
AI summary
Systems and methods for implementing data protection techniques with symbol-based variable node updates for binary low-density parity-check (LDPC) codes are described. A semiconductor memory (e.g., a NAND flash memory) may read a set of data from a set of memory cells, determine a set of data state probabilities for the set of data based on sensed threshold voltages for the set of memory cells, generate a valid codeword for the set of data using an iterative LDPC decoding with symbol-based variable node updates and the set of data state probabilities, and store the valid codeword within the semiconductor memory or transfer the valid codeword from the semiconductor memory. The iterative LDPC decoding may utilize a message passing algorithm in which outgoing messages from a plurality of multi-variable nodes are generated using incoming messages (e.g., log-likelihood ratios or L-values) from a plurality of check nodes.