Out-of-Order LDPC Layered Decoding for Parity Check Convergence
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Solution Overview
Problem
Existing data transfer systems face inefficiencies in error detection and correction, particularly in LDPC decoders, where the order of processing layers and circulants can lead to delays and reduced convergence speed, affecting the accuracy and speed of data decoding.
Innovation Solution
Implementing a multi-level layered LDPC decoding method with out-of-order processing, where layers are processed based on the number of unsatisfied parity checks and circulants are ordered to minimize dependencies, allowing for dynamic layer processing and reduced latency, and incorporating a low bit-width architecture to reduce memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If layers are processed in fixed order, then implementation is simple, but convergence speed is reduced due to delays
Solution Approach 1:
The patent implements dynamic layer processing where the processing order of layers is not fixed but adapts based on the number of unsatisfied parity checks. Layers with more unsatisfied checks are processed earlier, creating a dynamic scheduling system that optimizes convergence speed while managing complexity through adaptive rather than static ordering.
Solution Approach 2:
The patent changes the processing parameter by prioritizing layers based on the count of unsatisfied parity checks. This parameter-driven approach allows the system to dynamically adjust which layers are processed first, transforming a static processing sequence into a flexible, performance-optimized order that accelerates convergence.
2Loss of time
If circulants are processed in sequential order, then dependencies are maintained, but processing latency increases
Solution Approach 1:
The patent applies preliminary action by identifying and processing circulants that have no dependencies on previous layers before processing those with dependencies. This allows independent circulants to be processed in advance, reducing overall processing latency while systematically managing dependencies to maintain correctness.
Solution Approach 2:
The patent segments the circulant processing into distinct groups: circulants with no dependencies are separated and processed first, while circulants with dependencies are processed afterward. This segmentation allows parallel processing of independent units, reducing latency while maintaining proper dependency relationships.
3Reliability
If full bit-width architecture is used, then precision is maintained, but memory requirements increase
Solution Approach 1:
The patent changes the bit-width parameter by implementing a low bit-width architecture that uses reduced precision representations for check node processing. This parameter reduction decreases memory requirements while maintaining sufficient decoding accuracy through careful design of the reduced-precision operations.
Solution Approach 2:
The patent applies different precision levels to different parts of the decoding process. Full precision is maintained where critical for accuracy, while low bit-width representations are used in check node processing where approximate calculations are sufficient. This local quality approach optimizes the balance between memory usage and decoding reliability.
Data Source
AI summary
An apparatus for low density parity check decoding includes a variable node processor operable to generate variable node to check node messages and to calculate perceived values based on check node to variable node messages, a check node processor operable to generate the check node to variable node messages and to calculate checksums based on the variable node to check node messages, and a scheduler operable to determine a layer processing order for the variable node processor and the check node processor based at least in part on the number of unsatisfied parity checks for each of the H matrix layers.