LDPC Encoder Parity Address Updates for Faster Encoding

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Solution Overview

Problem

Current LDPC codes for terrestrial cloud transmission systems face challenges in spectrum efficiency due to co-channel interference and require efficient methods for updating parity bit addresses to improve encoding efficiency.

Innovation Solution

A new LDPC encoder and decoder system that updates parity bit addresses using a sequence corresponding to a parity check matrix (PCM), specifically employing equations to calculate new addresses for accumulation, enhancing the efficiency of LDPC encoding and decoding processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC codes are used for terrestrial cloud transmission, then error correction capability is provided, but spectrum efficiency deteriorates due to co-channel interference and white space generation

Engineering Contradiction:

Improveerror correction capabilityVSAvoidspectrum efficiency

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent applies parameter changes by modifying the parity check matrix structure from conventional forms to a dual-diagonal matrix form with specific circulant permutation patterns. This structural parameter change enables more efficient frequency reuse and reduces co-channel interference, thereby improving spectrum efficiency while maintaining error correction capability through the optimized LDPC code design

Inventive Principle:

Principle #35Parameter changes

2Productivity

If parity bit addresses are updated using conventional methods, then LDPC encoding can be performed, but encoding efficiency is reduced due to insufficient optimization in address update processes

Engineering Contradiction:

Improveencoding efficiencyVSAvoidencoding time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing the dual-diagonal matrix structure and circulant permutation patterns in the parity check matrix before encoding operations. This preliminary preparation allows the encoder to efficiently update parity bit addresses during actual encoding by simply referencing the pre-structured matrix, significantly reducing encoding time and improving overall encoding efficiency

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent changes the address update parameter methodology by transitioning from conventional sequential address updating to a pattern-based update approach that leverages the dual-diagonal matrix structure. This parameter change in the address update mechanism enables faster and more systematic parity bit generation, directly improving encoding productivity

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS9602243B2Low density parity check encoder, and low density parity check encoding method using the same

Publication Date: 2017.03.21 ELECTRONICS & TELECOMM RES INST

AI summary

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).