LDPC Encoder Parity Address Updating for DVB Spectrum Efficiency

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Solution Overview

Problem

Current LDPC codes for terrestrial broadcasting face challenges in spectrum efficiency due to co-channel interference, particularly in areas where frequency reuse is limited by white spaces, and existing LDPC codes do not provide specific encoding methods suitable for DVB broadcast standards.

Innovation Solution

A new LDPC code with lengths of 64800 or 16200, utilizing a sequence corresponding to a parity check matrix, efficiently updates parity bit addresses through accumulation, incorporating a dual diagonal matrix and identity matrix, to improve encoding efficiency and adaptability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC codes are used for terrestrial broadcasting, then error correction capability is provided, but spectrum efficiency deteriorates due to white space caused by co-channel interference

Engineering Contradiction:
Improveerror correction capabilityVSAvoidspectrum efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent changes the code length parameter from conventional values to specifically 64800 or 16200, which are optimized for terrestrial broadcasting to achieve both reliable error correction and improved spectrum efficiency through better frequency reuse

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces dynamic parity bit address updating during encoding using a sequence corresponding to a parity check matrix, allowing the encoder to adaptively manage parity bits and improve encoding efficiency for the specific code lengths, thereby enhancing overall system performance

Inventive Principle:
Principle #15Dynamics

2Productivity

If frequency reuse is implemented to improve spectrum efficiency, then co-channel interference increases making signal demodulation difficult

Engineering Contradiction:
Improvespectrum efficiencyVSAvoidsignal reception robustness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent optimizes the LDPC code parameters (code length of 64800 or 16200) specifically for terrestrial broadcasting scenarios, achieving a balance that allows frequency reuse while maintaining signal reception robustness through enhanced error correction capability tailored to the broadcasting channel characteristics

Inventive Principle:
Principle #35Parameter changes

3Reliability

If LDPC encoding is performed without specific optimization for DVB broadcast standards, then general error correction is provided, but encoding efficiency is not maximized for broadcasting applications

Engineering Contradiction:
Improveerror correctionVSAvoidencoding efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent specifies code lengths of 64800 or 16200 which are optimized for DVB broadcast standards, and employs a parity check matrix with dual diagonal structure that is specifically tailored to broadcasting applications, thereby maximizing encoding efficiency while maintaining error correction capability

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent implements dynamic parity bit address updating during the encoding process using a sequence corresponding to the parity check matrix, which optimizes the encoding operation for broadcasting applications and improves encoding efficiency compared to conventional static approaches

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10999004B2Low density parity check encoder, and low density parity check encoding method using the same
Publication Date: 2021.05.04 ELECTRONICS & TELECOMM RES INST
  • US10999004B2 patent drawing
  • US10999004B2 patent drawing
  • US10999004B2 patent drawing

AI summary

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).