LDPC Parity Bit Interleaving for Burst-Error-Resistant 256QAM
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Solution Overview
Problem
Current data transmission methods using LDPC codes face challenges in maintaining good communication quality due to errors and erasures, particularly in burst error environments, which affect decoding performance and increase power consumption.
Innovation Solution
The implementation of a transmission method that includes parity interleaving and block interleaving of LDPC codes, ensuring that parity bits are interleaved and distributed to prevent simultaneous errors at check nodes, thereby improving resistance to burst errors and maintaining performance in additive white Gaussian noise channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes are used for data transmission with quadrature modulation, then error correction capability is improved, but vulnerability to burst errors increases
Solution Approach 1:
The patent applies segmentation by dividing the LDPC code structure into information bits and parity bits, with the parity bits further organized into multiple groups. This segmentation allows selective interleaving of parity bits to specifically address burst error vulnerability while preserving the overall error correction capability of the LDPC code.
Solution Approach 2:
The patent introduces a new dimension of protection by applying bit interleaving specifically to parity bits, transforming the one-dimensional sequential structure into a two-dimensional arrangement where parity bits are distributed across different positions. This dimensional transformation enables the system to resist burst errors that affect consecutive bits.
2Object-affected harmful factors
If bit interleaving is applied to LDPC codes, then resistance to burst errors is improved, but decoding complexity increases
Solution Approach 1:
The patent applies local quality by implementing bit interleaving only for parity bits rather than all code bits. This localized approach provides burst error protection where it is most needed (in parity bits) while avoiding the increased complexity that would result from interleaving the entire code structure.
Solution Approach 2:
The patent applies partial action by performing bit interleaving on only a portion of the LDPC code (specifically the parity bits) rather than the complete code. This partial application achieves sufficient burst error resistance while maintaining manageable decoding complexity.
3Reliability
If parity bits are interleaved to prevent simultaneous errors, then decoding performance is improved, but processing time increases
Solution Approach 1:
The patent applies preliminary action by performing bit interleaving of parity bits before the actual data transmission and decoding process. This pre-processing arrangement ensures that parity bits are optimally positioned to prevent simultaneous errors, thereby improving decoding performance without adding time during the critical decoding phase.
Data Source
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AI summary
The present technology relates to a transmission method and a reception device capable of ensuring good communication quality in data transmission by using an LDPC code. In group-wise interleaving, an LDPC code with a code length N of 69120 bits is interleaved in units of bit groups of 360 bits. In group-wise deinterleaving, an arrangement of the LDPC code after the group-wise interleaving is returned to an original arrangement. The present technology can be applied, for example, to the case of performing data transmission by using an LDPC code or the like.