LDPC Parity-Check Matrix Structure for Practical Iterative Decoding
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Solution Overview
Problem
Current LDPC code technologies face challenges in designing parity-check matrices that optimize performance for high-speed digital communication systems, particularly in overcoming noise, fading, and inter-symbol interference, which affects data throughput and reliability.
Innovation Solution
The development of an LDPC encoding and decoding apparatus and method using a parity-check matrix with an information word sub-matrix and a parity sub-matrix, structured into column blocks and row blocks, defined by specific tables for different code rates, to enhance encoding and decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDPC codes are decoded by applying sum-product algorithm based iterative decoding to the LDPC codes on a tanner graph, then the performance of the LDPC codes approaches the Shannon's channel capacity, but the complexity which could hardly be implemented at the technology level increases
Solution Approach 1:
The parity check matrix is divided into multiple sub-matrices (first through fourth sub-matrices), each handling specific portions of the encoding/decoding process. This segmentation allows the complex decoding operation to be broken down into manageable sub-operations that can be implemented more easily while maintaining overall performance
Solution Approach 2:
The patent employs lifting-based construction where the base matrix is expanded using a lifting factor to create the full parity check matrix. By adjusting the lifting factor and the structure of the base matrix, the code rate and performance characteristics can be optimized while controlling the implementation complexity
2Reliability
If the parity-check matrix is designed to optimize performance for high-speed digital communication systems, then the error correction capability improves, but the design complexity and implementation difficulty increase
Solution Approach 1:
The parity check matrix is segmented into multiple sub-matrices with specific structures (some being identity matrices or having identity matrix sub-blocks). This structured segmentation enables systematic construction and simplifies the implementation of encoders and decoders while achieving optimal error correction performance
Solution Approach 2:
The patent uses code rate as a key parameter to determine the specific structure of the parity check matrix. Different code rates (e.g., 1/3, 2/3, 3/4) correspond to different matrix configurations, allowing the system to be optimized for specific application requirements while maintaining implementation feasibility
Data Source
AI summary
A transmitting apparatus encodes information bits using a low density parity check (LDPC) encoder, which is configured to encode information bits to generate parity bits based on a parity check matrix. In some embodiments, the code rate is 8/15 and the code length is 64800. The transmitting apparatus also includes an interleaver configured to interleave an LDPC codeword including the information bits and parity bits and a mapper configured to map the interleaved LDPC codeword onto constellation points. In some embodiments, the parity check matrix comprises an information matrix part corresponding to the information bits and a parity matrix part corresponding to the parity bits. In some embodiments, the information matrix part is defined by a specific table indicating indices of rows at which a value “1” is positioned in a 0-th column of an i-th column group in the parity check matrix.