LDPC Parity Interleaving for Burst-Error-Resistant Transmission
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Solution Overview
Problem
In data transmission using LDPC codes, existing technologies face challenges in maintaining favorable communication quality due to burst errors and erasures, particularly in AWGN channels and multipath environments, which affect the accuracy of decoding and increase power consumption.
Innovation Solution
The implementation of a transmission and reception system that employs a parity interleaving method to separate parity bits, combined with block and group-wise interleaving, to improve resistance to burst errors and maintain performance in AWGN channels, using a configuration that includes a bit interleaver, mapper, and LDPC encoder, and a reception system with a bit deinterleaver and LDPC decoder.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are not interleaved, then device complexity is reduced, but reliability deteriorates due to burst errors and erasures affecting decoding accuracy
Solution Approach 1:
The parity bits are segmented into multiple groups (first parity bit group and second parity bit group) and interleaved separately with different periods. This segmentation allows the system to handle burst errors more effectively by distributing them across different groups, improving decoding accuracy without requiring a completely complex interleaving structure.
Solution Approach 2:
The patent changes the interleaving period parameter - using a first interleaving period for the first parity bit group and a second interleaving period (different from the first) for the second parity bit group. This parameter variation optimizes the balance between error correction capability and structural complexity.
2Reliability
If interleaving is applied to protect against burst errors, then reliability improves, but power consumption increases due to additional processing
Solution Approach 1:
By dividing parity bits into multiple groups with different interleaving periods, the system achieves better burst error resistance while distributing the processing load. This segmentation prevents any single processing stage from becoming excessively complex and power-intensive.
Solution Approach 2:
Different portions of the parity bits (different groups) are treated with different interleaving periods, applying locally optimized error protection. This local quality approach ensures adequate protection against burst errors while minimizing overall processing complexity and power consumption.
Data Source
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AI summary
The present technology relates to a transmission device, a transmission method, a reception device, and a reception method for securing good communication quality in data transmission using an LDPC code. The LDPC coding is performed on the basis of the parity check matrix of the LDPC code with the code length N of 17280 bits and the coding rate r of 13/16 or 14/16. The LDPC code includes information bits and parity bits, and the parity check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits. The information matrix portion is represented by a parity check matrix initial value table, and the parity check matrix initial value table is a table representing positions of elements of 1 of the information matrix for every 360 columns. The present technology can be applied to, for example, data transmission using an LDPC code.