LDPC Parity Interleaving for Burst Error and Erasure Tolerance
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Solution Overview
Problem
LDPC codes face challenges in maintaining performance in communication paths with burst errors or erasure, particularly in OFDM systems with multi-path environments and ground wave communication, where conventional error correction methods are inadequate.
Innovation Solution
A data processing apparatus and method that incorporates parity interleave and column twist interleaving to re-arrange parity bits of LDPC codes, ensuring they are distributed in a staircase structure, thereby improving the tolerance to burst errors and erasure by spacing variable nodes connected to the same check node across multiple symbols.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If LDPC encoding is performed using a conventional parity check matrix, then encoding efficiency is improved, but tolerance to burst errors and erasure deteriorates
Solution Approach 1:
The parity bits are segmented and redistributed to different positions in the codeword according to a staircase pattern, rather than being concentrated in a single region. This segmentation prevents burst errors from affecting multiple parity bits simultaneously, thereby improving error tolerance while maintaining encoding efficiency.
Solution Approach 2:
The patent transforms the one-dimensional arrangement of parity bits into a two-dimensional staircase structure. By organizing parity bits in a staircase pattern across multiple dimensions of the codeword, the system achieves better dispersion of error-prone positions, improving tolerance to burst errors and erasure without sacrificing encoding performance.
2Reliability
If multiple decoding repetitions are performed to improve error correction, then error correction capacity is improved, but power consumption increases
Solution Approach 1:
The patent performs preliminary interleaving of parity bits in a staircase pattern before transmission. This preliminary arrangement ensures that even if decoding requires multiple repetitions, the error patterns are already dispersed in a way that facilitates faster convergence, thereby reducing the actual number of decoding iterations needed and lowering power consumption.
3Device complexity
If variable nodes connected to the same check node are spaced closely, then decoding complexity is reduced, but performance in burst error channels deteriorates
Solution Approach 1:
The patent introduces an asymmetric staircase structure for parity bit placement, where the distance between variable nodes connected to the same check node varies systematically rather than being uniform. This asymmetric spacing ensures that nodes are distributed to avoid clustering in error-prone regions, improving burst error performance while maintaining manageable decoding complexity through the structured pattern.
Data Source
AI summary
The present invention relates to a data processing apparatus and a data processing apparatus which can improve the tolerance to an error of a code bit of an LDPC code such as burst errors or erasure. An LDPC encoding section 21 carries out LDPC encoding in accordance with a parity check matrix in which a parity matrix which is a portion corresponding to parity bits of an LDPC (Low Density Parity Check) code has a staircase structure, and outputs an LDPC code. A parity interleaver 23 carries out parity interleave of interleaving the parity bits of the LDPC code outputted from the LDPC encoding section 21 to the positions of other parity bits. The present invention can be applied, for example, to a transmission apparatus which transmits an LDPC code.