LDPC Parity Interleaving for Burst-Resistant DVB OFDM Mapping
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Solution Overview
Problem
Existing OFDM communication systems face challenges in improving error correction performance, particularly in channels with correlated fading and burst errors, where LDPC codes struggle to maintain performance due to simultaneous errors in code bits connected to check nodes.
Innovation Solution
A data processing apparatus that combines a bit interleaver and a symbol interleaver to perform parity interleaving on LDPC encoded data bits, ensuring parity bits are interleaved to different positions and using a linear feedback shift register with a permutation circuit to generate addresses for mapping data symbols onto OFDM sub-carrier signals, optimizing the distribution of data symbols across sub-carriers to enhance error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data symbols are mapped onto OFDM sub-carrier signals without parity interleaving, then the mapping process is simple and fast, but error correction performance deteriorates in channels with correlated fading and burst errors
Solution Approach 1:
The patent divides the LDPC code into information bits and parity bits, applying different interleaving strategies to each segment. The parity bits are interleaved separately from information bits using a specific permutation pattern, which separates error-prone parity bits from their corresponding information bits. This segmentation allows the system to maintain simple overall structure while improving error correction through targeted parity bit distribution.
Solution Approach 2:
The patent applies local quality by using different interleaving approaches for different parts of the code. Specifically, parity bits undergo a distinct interleaving process with a permutation pattern of (15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) that is optimized for their error protection needs, while information bits are handled differently. This localized optimization improves overall reliability without requiring complete re-interleaving of all bits.
2Reliability
If a complex interleaving scheme is used to improve error correction performance, then reliability increases, but processing time and computational complexity increase
Solution Approach 1:
The patent performs parity interleaving as a preliminary action during the encoding stage, before transmission. By pre-processing the parity bits with a deterministic permutation pattern, the system prepares the code structure to be more resilient to burst errors without requiring complex real-time processing during decoding. This preliminary arrangement of parity bits ensures that even if burst errors occur, the affected bits are distributed in a way that maintains decodability.
3Reliability
If parity bits are not interleaved to different positions, then the interleaving process is simpler, but simultaneous errors in code bits connected to check nodes reduce decoding performance
Solution Approach 1:
The patent changes the positional parameters of parity bits through a specific permutation operation. The parity bits are rearranged according to a predetermined pattern that maps them to different positions in the transmitted sequence. This parameter change ensures that parity bits connected to the same check node are separated in the transmission stream, preventing simultaneous errors from affecting multiple parity bits associated with the same check constraint, thereby improving decoding performance.
Data Source
AI summary
A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals.