LDPC Parity And Group Interleaving for 1024-QAM Reception

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Solution Overview

Problem

There is a need for improved methods to support robust encoding, decoding, and receiving performance in digital broadcasting services, particularly for higher quality digital televisions and portable multimedia players, which existing technologies have not adequately addressed.

Innovation Solution

A transmitting apparatus and method that uses Low Density Parity Check (LDPC) coding, including an encoder to generate LDPC codewords, an interleaver to rearrange bit groups, and a modulator to map bits onto modulation symbols, specifically employing a parity interleaver, group interleaver, and block interleaver to enhance decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional encoding and modulation methods are used, then device complexity is reduced, but decoding and receiving performance are insufficient for high-quality digital broadcasting

Engineering Contradiction:
Improvedecoding performanceVSAvoidinterleaving structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The interleaver is divided into three distinct functional modules: parity interleaver, group interleaver, and block interleaver. Each module performs a specific aspect of bit rearrangement, allowing the system to achieve improved decoding performance through coordinated multi-stage processing while maintaining manageable complexity through functional decomposition

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different interleaving strategies are applied to different portions of the LDPC codeword: parity bits undergo specific permutation to improve error correction, information bits are grouped and rearranged to enhance robustness against burst errors. This localized optimization of interleaving quality for different bit types improves overall receiving performance

Inventive Principle:
Principle #3Local quality

2Reliability

If bit groups are rearranged using multiple interleaving stages, then robustness against channel errors is improved, but processing time and complexity increase

Engineering Contradiction:
Improverobustness against channel errorsVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The parity interleaver performs preliminary rearrangement of parity bits before the main group interleaving process. This preliminary action ensures that parity information is optimally positioned to handle potential error patterns, reducing the need for iterative decoding and thereby decreasing overall processing time despite the additional stage

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The interleaving process dynamically adapts to different channel conditions and error patterns by selectively applying different interleaving depths and patterns. This dynamic approach allows the system to achieve high robustness when needed while reducing processing overhead in favorable conditions

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10749548B2Transmitting apparatus and interleaving method thereof
Publication Date: 2020.08.18 SAMSUNG ELECTRONICS CO LTD
  • US10749548B2 patent drawing
  • US10749548B2 patent drawing
  • US10749548B2 patent drawing

AI summary

Provided is a signal interleaving method which includes: interleaving parity bits by encoding input bits based on a low density parity check (LDPC) code according to a code rate of 6/15 and a code length of 64800; splitting a codeword comprising the input bits and the interleaved parity bits into a plurality of bit groups; interleaving the plurality of bit groups according to a specific permutation order to provide an interleaved codeword; de-multiplexing bits of the interleaved codeword to generate data cells; mapping the data cells onto constellation points for 1024-quadrature amplitude modulation (QAM); and transmitting a signal based on the constellation points.