LDPC Parity and Group Interleaving for 256QAM Burst Errors

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Solution Overview

Problem

Current data transmission methods using LDPC codes face challenges in maintaining favorable communication quality, particularly due to burst errors and erasures in communication paths, which degrade decoding performance and increase power consumption.

Innovation Solution

The implementation of a transmission method that includes parity interleaving and group-wise interleaving, along with a specific configuration of the parity check matrix, to separate parity bits and distribute error resistance across the transmission system, thereby improving resistance to burst errors and maintaining performance in AWGN channels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional transmission methods are used without specific interleaving, then device complexity is reduced, but communication quality deteriorates due to burst errors and erasures

Engineering Contradiction:
Improvecommunication qualityVSAvoidinterleaving complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the code bits into multiple bit groups and applying different interleaving operations to different segments. Specifically, the LDPC code bits are divided into bit groups, with parity bits in one group and information bits in another, allowing targeted interleaving strategies for each segment to improve error resistance while managing complexity.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements preliminary action through parity interleaving performed before group-wise interleaving. The parity bits are interleaved within their bit group first, which prepares the code structure to better resist burst errors before the subsequent group-wise interleaving operation is applied to the entire code.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If no bit interleaving is applied, then device complexity is low, but decoding performance deteriorates under burst errors and erasures

Engineering Contradiction:
Improvedecoding performanceVSAvoidinterleaving structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the LDPC code into distinct bit groups for targeted interleaving. The parity bit group and information bit group are processed differently through the interleaving structure, allowing the system to achieve improved decoding performance under burst errors and erasures by applying appropriate interleaving to each segment.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent performs preliminary parity interleaving before group-wise interleaving to prepare the code structure for better error resistance. This preliminary action on the parity bits specifically enhances the code's ability to withstand burst errors and erasures before the final group-wise interleaving is applied.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If standard LDPC coding is used without optimized interleaving, then ease of operation is maintained, but power consumption increases due to repeated decoding attempts

Engineering Contradiction:
Improvepower consumptionVSAvoidtransmission method complexity
Core Design Contradiction:
Use of energy by moving objectVSEase of operation

Solution Approach 1:

The patent applies preliminary action by performing parity interleaving before group-wise interleaving, which optimizes the code structure in advance to better resist burst errors and erasures. This preliminary optimization reduces the need for repeated decoding attempts, thereby lowering power consumption while maintaining operational simplicity.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the interleaving parameters by applying different interleaving operations to different bit groups. The parity interleaving uses specific permutation patterns that are optimized for error resistance, and these parameter changes enable more efficient decoding with reduced power consumption.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentEP3579427B1Bit interleaving for LDPC codes of length 69120 and rate 3/16 in combination with 256qam
Publication Date: 2022.10.26 SONY GROUP CORP
  • EP3579427B1 patent drawingFigure 1~2
  • EP3579427B1 patent drawingFigure 3
  • EP3579427B1 patent drawingFigure 4

AI summary

The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.