LDPC Bit Interleaving Layout for 4096QAM Burst Error Dispersion
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Solution Overview
Problem
Current data transmission methods using LDPC codes face challenges in maintaining favorable communication quality, particularly due to burst errors and erasures in communication paths, which degrade decoding performance and increase power consumption.
Innovation Solution
The implementation of a transmission method that includes parity interleaving and group-wise interleaving, along with a specific configuration of the parity check matrix, to separate parity bits and distribute error resistance across the transmission system, thereby improving resistance to burst errors and maintaining performance in AWGN channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transmission methods are used without specific interleaving, then device complexity is reduced, but communication quality deteriorates due to burst errors and erasures
Solution Approach 1:
The patent applies segmentation by dividing the interleaving process into distinct stages: parity interleaving that separates parity bits into different groups, followed by group-wise interleaving that further distributes bits within each group. This multi-stage segmentation approach effectively disperses burst errors across different code bits, preventing concentrated error patterns that would degrade decoding performance, while maintaining manageable complexity through systematic organization of the interleaving operations.
Solution Approach 2:
The patent implements preliminary action by performing parity interleaving before group-wise interleaving. The parity bits are预先 distributed into different groups based on their positions modulo the number of parity bits, creating a preliminary error distribution pattern that enhances resistance to burst errors. This preliminary organization of parity bits before the main interleaving process establishes a foundation that improves overall communication quality without requiring complete re-design of the interleaving system.
2Reliability
If advanced interleaving techniques are implemented, then resistance to burst errors improves, but power consumption increases due to additional processing
Solution Approach 1:
The patent applies parameter changes by systematically varying the distribution parameters of parity bits across different groups. Specifically, parity bits at positions satisfying certain modulo conditions are distributed to different groups, creating a parameter-based distribution pattern. This approach achieves enhanced burst error resistance through mathematical parameter optimization rather than requiring complex additional processing circuits, thereby limiting the increase in power consumption while improving reliability.
3Ease of manufacture
If parity bits are concentrated in specific positions, then encoding simplicity is maintained, but error resistance deteriorates under burst error conditions
Solution Approach 1:
The patent resolves this contradiction by segmenting the parity bit positions into multiple groups based on positional parameters. Parity bits are distributed to different groups according to whether their positions satisfy specific modulo conditions, rather than being concentrated in a single location. This segmentation maintains encoding simplicity through systematic position-based rules while simultaneously improving error resistance by ensuring that burst errors affecting one group do not impact all parity bits.
Solution Approach 2:
The patent applies local quality by creating different distribution patterns for parity bits in different positional groups. Each group has specific quality characteristics in terms of error resistance, with parity bits in different groups experiencing different error patterns under burst conditions. This local differentiation of parity bit qualities through position-based distribution enhances overall system reliability while maintaining relatively simple encoding procedures through localized distribution rules.
Data Source
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AI summary
The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.