LDPC Parity Group Interleaving for Variable-Length Signaling

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Solution Overview

Problem

Existing channel encoding and modulation techniques for signaling information in broadcast systems are not robust enough, necessitating improved methods for efficient transmission.

Innovation Solution

A parity interleaving apparatus and method that segments parity bits of an LDPC codeword into groups and applies group-wise interleaving, optimized for signaling information transmission, including zero-padding and puncturing processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional channel encoding and modulation techniques are used for signaling information transmission, then the transmission process is simple, but the robustness and reliability of transmission deteriorates

Engineering Contradiction:
Improvetransmission robustnessVSAvoidencoding complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The parity bits are segmented into multiple groups (first parity bit group, second parity bit group, third parity bit group) with different puncturing rates applied to each group. This segmentation allows differential protection levels for different portions of parity information, improving overall transmission robustness while managing complexity through structured organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different puncturing rates are applied to different parity bit groups based on their importance. The first parity bit group uses a first puncturing rate, the second group uses a second puncturing rate, and the third group uses a third puncturing rate. This local differentiation optimizes reliability for critical signaling information while controlling overall system complexity

Inventive Principle:
Principle #3Local quality

2Productivity

If parity bits are not punctured, then transmission reliability is maintained, but transmission efficiency and bandwidth utilization deteriorates

Engineering Contradiction:
Improvetransmission efficiencyVSAvoidtransmission robustness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Instead of transmitting all parity bits or none, the invention applies partial puncturing with different rates to different parity groups. This partial action approach removes only the least critical parity bits (third group with highest puncturing rate) while preserving more robustly protected parity bits (first group with lowest puncturing rate), achieving optimal balance between efficiency and reliability

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The invention changes the puncturing rate parameter differently for each parity bit group. By varying the puncturing rate parameter across groups (first rate < second rate < third rate), the system adapts the transmission efficiency-reliability tradeoff to the specific requirements of different parity information portions

Inventive Principle:
Principle #35Parameter changes

3Stability of the object's composition

If variable-length signaling information is transmitted without zero-padding, then information fidelity is preserved, but encoding and transmission process becomes inconsistent

Engineering Contradiction:
Improveencoding consistencyVSAvoidinformation length
Core Design Contradiction:
Stability of the object's compositionVSQuantity of substance

Solution Approach 1:

Zero-padding is performed preliminarily on variable-length signaling information before LDPC encoding to standardize the input length. This preliminary action ensures that the encoding process receives consistent fixed-length input, improving encoding consistency and stability while the actual signaling information content remains intact for recovery at the receiver

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12375106B2Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same
Publication Date: 2025.07.29 ELECTRONICS & TELECOMM RES INST
  • US12375106B2 patent drawing
  • US12375106B2 patent drawing
  • US12375106B2 patent drawing

AI summary

A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.