LDPC Parity Bit Buffering for Faster HARQ Redundancy Versions
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Solution Overview
Problem
Current low-density parity check (LDPC) codes in wireless communication systems face challenges in efficiently managing parity bits for retransmissions in hybrid automatic repeat request (HARQ) schemes, leading to increased latency and hardware inefficiencies due to the need to regenerate all parity bits for subsequent redundancy versions.
Innovation Solution
Storing at least the degree-two and degree-three parity bits from the initial transmission in a memory, such as a HARQ buffer or upper layer buffer, to reduce latency and improve hardware efficiency by reusing these stored parity bits for generating subsequent redundancy versions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all parity bits are regenerated for subsequent redundancy versions, then decoding reliability is maintained, but latency increases and hardware efficiency deteriorates
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing degree-two and degree-three parity bits during the initial encoding phase. These pre-computed parity bits are stored in a buffer for subsequent retransmissions, eliminating the need to regenerate them during HARQ operations. This advance preparation reduces latency while maintaining decoding reliability through selective reuse of pre-computed redundancy information.
Solution Approach 2:
The patent segments the parity bits into different categories based on their generation degree (degree-one, degree-two, degree-three). This segmentation allows selective storage and reuse of only the degree-two and degree-three parity bits, which are most beneficial for reducing latency, while maintaining the ability to regenerate other parity bits as needed. This selective approach balances reliability and efficiency.
2Reliability
If all parity bits are regenerated for subsequent redundancy versions, then complete redundancy information is available, but hardware complexity and computational load increase
Solution Approach 1:
The patent extracts and isolates the degree-two and degree-three parity bits from the complete set of parity bits generated during LDPC encoding. By extracting only these specific parity bits for storage in the HARQ buffer, the system reduces the computational burden and hardware resources required for retransmissions, while still providing sufficient redundancy information to maintain reliability through selective reuse.
3Reliability
If degree-one parity bits are stored for subsequent versions, then more redundancy information is available, but memory requirements and buffer size increase
Solution Approach 1:
The patent applies local quality by assigning different storage policies to different types of parity bits based on their specific characteristics and usefulness for retransmission. Degree-two and degree-three parity bits are stored in the HARQ buffer because they provide the most benefit for reducing latency and improving efficiency. Degree-one parity bits are excluded from storage to minimize memory requirements, as they can be efficiently regenerated when needed. This localized optimization balances redundancy availability with memory constraints.
Data Source
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AI summary
Aspects of the present disclosure relate to low density parity check (LDPC) encoding. At least a portion of the parity bits generated by an LDPC encoder for an initial transmission may be stored for use in generating subsequent hybrid automatic repeat request (HARQ) redundancy versions. In some examples, at least the degree-two and degree-three parity bits included in the initial transmission may be stored. The parity bits may be stored within a layer 2 (L2) or an upper layer buffer or within the LDPC encoder. For example, the parity bits may be stored within the HARQ buffer.