LDPC Parity Interleaving for Robust Variable-Length Signaling

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Solution Overview

Problem

Current channel encoding and modulation techniques for signaling information in broadcast systems lack robustness and efficiency, necessitating the development of new methods optimized for signaling information transmission.

Innovation Solution

A parity interleaving technique is introduced, involving a processor to generate and segment parity bits of an LDPC codeword into groups for group-wise interleaving and puncturing, optimized for the transmission of signaling information, using specific sequences and calculations for puncturing sizes based on modulation order and codeword lengths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional channel encoding and modulation techniques are used for signaling information transmission, then the system maintains simplicity and compatibility with existing standards, but the robustness and transmission reliability of signaling information deteriorates

Engineering Contradiction:
Improverobustness of signaling information transmissionVSAvoidcomplexity of channel encoding and modulation system
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The LDPC codeword is segmented into multiple groups (e.g., 36 groups of 360 bits each), and group-wise interleaving is applied to permute these groups according to a specific sequence. This segmentation approach enhances robustness by distributing signaling information across multiple segments, preventing concentrated errors while maintaining manageable processing complexity through structured group operations.

Inventive Principle:
Principle #1Segmentation

2Productivity

If fixed-length LDPC codewords are used for variable-length signaling information, then the encoding structure remains simple and standardized, but the efficiency of signaling information transmission deteriorates due to unnecessary zero-padding and fixed puncturing

Engineering Contradiction:
Improvetransmission efficiency of signaling informationVSAvoidamount of transmitted bits including padding
Core Design Contradiction:
ProductivityVSQuantity of substance

Solution Approach 1:

The system dynamically adjusts the puncturing size based on the actual length of signaling information. The puncturing amount is calculated as a function of the difference between the fixed LDPC codeword length (16200 bits) and the actual signaling information length, allowing the system to transmit variable-length signaling information efficiently while maintaining the standardized LDPC encoding framework. This dynamic adjustment eliminates unnecessary transmission of padded zeros.

Inventive Principle:
Principle #15Dynamics

3Reliability

If group-wise interleaving with specific sequences is applied to parity bits, then the error correction capability and robustness improve, but the processing complexity and computational load increase

Engineering Contradiction:
Improveerror correction capabilityVSAvoidprocessing complexity of parity interleaving
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

A predetermined group-wise interleaving sequence is defined and stored in advance (e.g., a specific permutation of 36 group indices). This preliminary preparation allows the interleaving operation to be executed efficiently during transmission without real-time complex calculations. The receiver uses the same predetermined sequence to perform de-interleaving, ensuring synchronization while minimizing processing complexity through pre-computed lookup tables.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10333553B2Parity interleaving apparatus for encoding variable-length signaling information and parity interleaving method using same
Publication Date: 2019.06.25 ELECTRONICS & TELECOMM RES INST
  • US10333553B2 patent drawing
  • US10333553B2 patent drawing
  • US10333553B2 patent drawing

AI summary

A parity interleaving apparatus and method for variable length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.