LDPC Parity Permutation Layout for Punctured Broadcast Decoding
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current signal transmitters and receivers in digital broadcasting face challenges in providing improved performance and efficiency, particularly in high-definition digital TV and portable broadcasting, due to limitations in parity bit management and transmission schemes.
Innovation Solution
A transmitter equipped with a Low Density Parity Check (LDPC) encoder, parity permutator, and puncturer performs parity permutation by interleaving and puncturing parity bits to enhance signal transmission efficiency, specifically using a scheme that positions some bit groups at predetermined positions and randomizes the remainder within group-wise interleaved bit groups.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are transmitted without permutation, then the transmission scheme is simple, but the decoding performance and error correction capability are insufficient
Solution Approach 1:
The patent applies preliminary action by performing parity permutation in advance before transmission. The transmitter reorders parity bits according to a predetermined pattern, and the receiver applies the corresponding inverse permutation during decoding. This preliminary reordering improves error correction capability by distributing burst errors more uniformly, while the predetermined pattern ensures the complexity increase is manageable and predictable.
Solution Approach 2:
The patent segments the parity bits into multiple groups and applies different permutation patterns to different segments. This segmentation allows the system to improve decoding performance for specific error patterns while maintaining a structured approach that limits overall complexity. Each segment can be independently permuted and processed.
2Productivity
If all parity bits are transmitted, then error correction capability is maximized, but transmission efficiency is reduced due to excessive redundancy
Solution Approach 1:
The patent extracts and removes certain parity bits from the transmitted signal through puncturing. By selectively removing redundant parity bits that provide diminishing returns on error correction capability, the system increases transmission efficiency. The receiver compensates for the removed bits by using the permutation information and remaining parity bits to reconstruct the necessary check information.
Solution Approach 2:
The patent applies partial action by transmitting only a subset of the full set of parity bits. Instead of transmitting all generated parity bits, the system transmits a carefully selected portion that provides sufficient error correction for the expected channel conditions, thereby improving transmission efficiency while maintaining adequate reliability.
3Productivity
If parity bits are punctured without specific positioning, then transmission efficiency improves, but decoding performance deteriorates due to loss of critical parity information
Solution Approach 1:
The patent applies local quality by treating different parity bit positions differently. Certain positions are designated to hold specific types of parity bits that are more critical for decoding performance. The permutation pattern ensures that important parity information is placed in protected positions that are less likely to be punctured, while less critical positions can be punctured to improve efficiency.
Solution Approach 2:
The patent uses preliminary action by pre-determining the permutation pattern that identifies which positions will hold critical parity information. This predetermined pattern allows the transmitter to strategically place important parity bits in positions that will be preserved during transmission, while allowing less critical positions to be punctured for efficiency.
Data Source
AI summary
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to puncture some of the parity bits in the group-wise interleaved bit groups, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups.