LDPC Parity Block Layout for Multi-Level Memory Cells

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Solution Overview

Problem

LDPC parity calculation presents challenges in non-integer power of 2 number of cell levels situations, requiring additional storage capacity or encoding, which is not desirable.

Innovation Solution

Applying modulation coding to user bits, generating and storing parity bits in separate modulation blocks, and embedding parity data within these blocks to maintain data integrity without excessive storage usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If LDPC parity calculation is performed for non-integer power of 2 number of cell levels, then data integrity is maintained, but additional storage capacity is required

Engineering Contradiction:
Improvedata integrityVSAvoidstorage capacity
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The user data is divided into multiple portions, with each portion having its own separate modulation block and parity block. This segmentation allows parity bits to be distributed across different blocks rather than requiring集中 storage, thereby maintaining data integrity while optimizing storage capacity utilization.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a new dimension by creating separate modulation blocks and parity blocks as distinct storage units. This dimensional separation allows the system to store parity information efficiently without overloading a single storage block, resolving the contradiction between maintaining integrity and managing storage capacity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If LDPC parity data is encoded for non-integer power of 2 number of cell levels, then storage capacity is reduced, but encoding complexity increases

Engineering Contradiction:
Improvestorage capacityVSAvoidencoding complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

Instead of encoding the parity data to reduce storage capacity, the patent inverts the approach by using separate modulation blocks that naturally accommodate the parity bits without additional encoding. This reversal eliminates the encoding complexity while still optimizing storage capacity through the segmented block structure.

Inventive Principle:
Principle #13The other way round (Inversion)

3Quantity of substance

If separate modulation blocks are used for user data and parity data, then storage capacity is optimized, but device complexity increases

Engineering Contradiction:
Improvestorage capacityVSAvoiddevice complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The separate modulation blocks and parity blocks serve multiple functions: they enable efficient storage capacity utilization, facilitate error detection and correction, and support non-integer power of 2 cell levels. This multi-functionality justifies the increased device complexity by delivering multiple benefits simultaneously.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS11487611B2LDPC encoding for memory cells with arbitrary number of levels
Publication Date: 2022.11.01 SANDISK TECHNOLOGIES LLC
  • US11487611B2 patent drawing
  • US11487611B2 patent drawing
  • US11487611B2 patent drawing

AI summary

The present disclosure generally relates to applying LDPC coding to memory cells with an arbitrary number of levels. Modulation code is applied to a first portion of user bits. The coded user data is stored in a first modulation block. Parity bits are then generated for the first portion of user bits. The parity bits are then stored in a second modulation block different from the first modulation block. Modulation code is then applied to a second portion of user bits which are stored in the second modulation block. Parity bits are then generated for the second portion of user bits and stored in a third modulation block. The parity bits are thus embedded in a separate modulation block from the modulation block where the user data is stored.