LDPC Parity Bits for NVM Erase Cell Interference
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Solution Overview
Problem
In non-volatile memory (NVM) dies, error-prone 'erase cells' can electrically affect adjacent good memory cells, causing data corruption, and existing methods to mitigate this issue, such as additional screening or custom trim parameters, are time-consuming and costly, lowering yield and delaying product launches.
Innovation Solution
Implementing a Low Density Parity Check (LDPC) engine to generate parity bits for good memory cells, which corrects errors when data is requested, by identifying and masking out erase cells and using ECC codes to mitigate the effects of bit flips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If additional screening is performed to remove erase cells, then data reliability is improved, but manufacturing time increases and yield decreases
Solution Approach 1:
The system performs preliminary identification and classification of memory cells as erase cells or good cells during manufacturing. By pre-categorizing cells and their locations, the system enables subsequent error correction without requiring additional screening time, thus maintaining yield while ensuring reliability through proactive error prevention.
Solution Approach 2:
The patent introduces an intermediary error correction mechanism that acts between the erase cells and adjacent good cells. By using parity bits and error correction codes as intermediaries, the system mitigates the harmful electrical effects of erase cells without needing to physically remove or screen them, thereby maintaining manufacturing efficiency while protecting data integrity.
2Reliability
If custom trim parameters are developed to electrically tune the die, then data reliability is improved, but development time and resources increase
Solution Approach 1:
The system implements self-service error correction where the memory device automatically identifies and corrects errors caused by erase cells using built-in parity bits and error correction codes. This eliminates the need for external custom trim parameter development, as the device autonomously manages its own reliability issues without requiring time-consuming manual tuning or resource-intensive optimization processes.
3Ease of manufacture
If erase cells are logically separated from good memory cells, then manufacturing simplicity is maintained, but electrical interference causes bit flips in adjacent cells
Solution Approach 1:
The patent converts the harmful electrical interference from erase cells into a beneficial error correction opportunity. By accepting that bit flips will occur and using parity bits to detect and correct these errors, the system transforms the harmful effect of erase cell interference into a manageable and correctable condition, maintaining manufacturing simplicity while ensuring data integrity.
Data Source
AI summary
Methods and systems for increasing reliability of a data storage device are disclosed. During fabrication runs of a non-volatile memory (NVM) die, such as a NAND, there may be a number of memory cells designated as erase cells. When one or more erase cells are physically adjacent to programmed memory cell, electrical effects of the erase cell may cause a bit to flip in the adjacent good memory cell. To mitigate this effect, an LDPC engine is used to generate additional parity bits for the erased bit/cells. When a host requests data from the NVM, the parity bits may be used to correct additional errors because of the erased state to programmed state bit flips.