LDPC Parity Interleaving for OFDM Burst-Error Resistance
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Solution Overview
Problem
Existing OFDM communication systems, particularly in DVB-T and DVB-H standards, face challenges in improving error correction performance due to correlated fading in terrestrial broadcast channels, which affects the integrity of data communication, especially when using LDPC codes, and there is a need to enhance resistance to burst errors and erasures while maintaining performance in AWGN communication paths.
Innovation Solution
A transmitter is developed that incorporates a parity interleaver for LDPC encoded data bits using a stepwise-structured parity matrix, combined with a symbol interleaver and an address generator, which includes a linear feedback shift register and permutation circuit to effectively map data symbols onto OFDM sub-carrier signals, optimizing the distribution of parity bits and data symbols for improved error correction and resistance to burst errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data symbols are mapped directly onto sub-carrier signals without interleaving, then the mapping process is simple and fast, but error correction performance deteriorates due to correlated fading in terrestrial broadcast channels
Solution Approach 1:
The patent divides the interleaving process into two independent segments: bit-level interleaving for LDPC codes and symbol-level interleaving for OFDM symbols. This segmentation allows each interleaver to be optimized for its specific function, improving error correction performance while maintaining manageable complexity through modular design
Solution Approach 2:
The patent implements a nested structure where the bit interleaver operates on LDPC encoded bits first, and then the symbol interleaver processes the resulting data symbols. This nested approach enables hierarchical error protection where bit-level diversity is established before symbol-level distribution, achieving enhanced reliability without requiring a completely new complex system
2Reliability
If parity bits are concentrated in specific positions for LDPC encoding, then encoding efficiency is improved, but resistance to burst errors deteriorates due to correlated fading affecting adjacent sub-carriers
Solution Approach 1:
The patent applies local quality by implementing position-dependent interleaving patterns where parity bits and information bits are distributed to different sub-carrier positions based on their specific requirements. The stepwise parity matrix structure ensures that parity bits are strategically placed in positions that maximize diversity protection against burst errors while maintaining encoding efficiency
Solution Approach 2:
The patent transitions from one-dimensional sequential bit mapping to two-dimensional mapping by introducing both bit-level and symbol-level interleaving dimensions. This dimensional expansion allows parity bits to be dispersed across multiple dimensions (different bits, different symbols, different sub-carriers), providing enhanced protection against burst errors without sacrificing encoding efficiency
3Reliability
If data symbols are separated onto different sub-carrier signals by large intervals, then error correction performance is improved through diversity, but the bandwidth utilization and transmission efficiency deteriorate
Solution Approach 1:
The patent implements dynamic interleving patterns that adapt the separation intervals between data symbols based on channel conditions and transmission requirements. The address generator uses pseudo-random sequences to create variable spacing patterns, providing diversity protection while maintaining flexible bandwidth utilization and transmission efficiency
Data Source
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AI summary
A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals. A symbol interleaver is arranged in operation to read-into a symbol interleaver memory the predetermined number of data symbols for mapping onto the OFDM sub-carrier signals, and to read-out of the interleaver memory the data symbols for the OFDM sub-carriers to effect the mapping, the read-out being in a different order than the read-in, the order being determined from a set of addresses, with the effect that the data symbols are interleaved on the sub-carrier signals. The set of addresses are generated by an address generator which has been optimised to interleave the data symbols on to the sub-carrier signals of the OFDM carrier signals for a given operating mode of the OFDM system, such as a 32K operating mode for DVB-T2 or DVB-C2.