LDPC Parity Permutation Layout for Better Broadcast Decoding

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Solution Overview

Problem

Current signal transmitters and receivers in digital broadcasting face challenges in providing improved performance and efficient signal transmission and reception, particularly in high-definition digital television and portable broadcasting, due to limitations in existing parity permutation methods.

Innovation Solution

A transmitter equipped with a Low Density Parity Check (LDPC) encoder, a parity permutator, and a puncturer performs parity permutation by interleaving and puncturing parity bits, optimizing their placement to enhance decoding performance and error correction in digital broadcasting.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If parity bits are transmitted without permutation, then the transmission structure is simple, but decoding performance and error correction are insufficient

Engineering Contradiction:
Improvedecoding performanceVSAvoidpermutation structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The parity bits are divided into multiple groups (first parity bit group, second parity bit group, third parity bit group) and each group is permuted separately using different patterns. This segmentation allows the system to improve decoding performance through structured permutation while maintaining manageable complexity by processing each group independently rather than permuting all parity bits as a single large block.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different permutation patterns are applied to different parity bit groups based on their specific characteristics and positions. The first parity bit group uses a first permutation pattern, the second group uses a second pattern, and the third group uses a third pattern. This local differentiation optimizes error correction for each group's specific error patterns while avoiding the need for a single complex universal permutation scheme.

Inventive Principle:
Principle #3Local quality

2Productivity

If all parity bits are transmitted, then error correction capability is maximized, but transmission efficiency is reduced due to excessive redundancy

Engineering Contradiction:
Improvetransmission efficiencyVSAvoiderror correction capability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The system extracts and transmits only the essential parity bit groups after permutation, rather than transmitting all generated parity bits. By applying permutation to organize the parity bits into structured groups and selectively transmitting relevant groups, the system removes redundant parity bits that would not contribute significantly to error correction, thereby improving transmission efficiency while maintaining adequate error correction capability.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If parity bits are randomly distributed, then placement flexibility is high, but decoding performance is inconsistent

Engineering Contradiction:
Improvedecoding performanceVSAvoidpermutation pattern design
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The system applies predetermined permutation patterns to organize parity bits into specific groups before transmission. These patterns are designed in advance to distribute parity bits in optimal positions that maximize decoding performance. By performing this organization action preliminarily at the transmitter side using defined patterns, the system ensures consistent decoding performance at the receiver without requiring complex real-time decision-making or adaptive algorithms.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12160251B2Transmitter and parity permutation method thereof
Publication Date: 2024.12.03 SAMSUNG ELECTRONICS CO LTD
  • US12160251B2 patent drawing
  • US12160251B2 patent drawing
  • US12160251B2 patent drawing

AI summary

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to puncture some of the parity bits in the group-wise interleaved bit groups, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups.