LDPC Parity Permutation Layout for Sequential Puncturing

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Solution Overview

Problem

Current digital broadcasting systems face challenges in providing improved performance and efficient signal transmission and reception, particularly in high-definition digital television and portable broadcasting, due to limitations in existing transmitter and receiver technologies.

Innovation Solution

A transmitter equipped with a Low Density Parity Check (LDPC) encoder, parity permutator, and puncturer performs parity permutation by group-wise interleaving and puncturing of parity bits, optimizing the order and selection of parity bits for improved decoding performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If parity bits are transmitted without permutation, then the transmission process is simple, but decoding performance is insufficient

Engineering Contradiction:
Improvedecoding performanceVSAvoidtransmitter structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The parity bits are divided into multiple groups (first parity bit group, second parity bit group, third parity bit group) and processed differently. Some groups are permuted while others are not, allowing selective application of complexity to achieve decoding performance improvements without unnecessarily complicating the entire transmission process.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different quality treatments are applied to different parts of the parity bits. Specifically, certain parity bit groups undergo permutation operations while others remain in original order, creating local variations in bit arrangement that improve overall decoding performance without applying uniform complexity across all bits.

Inventive Principle:
Principle #3Local quality

2Productivity

If all parity bits are transmitted, then decoding accuracy is maintained, but transmission efficiency decreases

Engineering Contradiction:
Improvetransmission efficiencyVSAvoiddecoding accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Certain parity bit groups are extracted and permuted to specific positions in the transmitted signal, while other parity bit groups are left in their original positions. This selective extraction and repositioning allows the system to maintain necessary redundancy for decoding accuracy while optimizing the arrangement for improved transmission efficiency.

Inventive Principle:
Principle #2Taking out (Extraction)

3Adaptability or versatility

If parity bits are permuted randomly, then bit group diversity is increased, but decoding reliability deteriorates

Engineering Contradiction:
Improvebit group arrangement flexibilityVSAvoiddecoding reliability
Core Design Contradiction:
Adaptability or versatilityVSReliability

Solution Approach 1:

The permutation operation is performed in advance on specific parity bit groups before transmission, with predetermined positioning rules. The first and second parity bit groups are permuted to specific positions, while the third parity bit group maintains its original position. This preliminary, structured arrangement provides adaptability in bit group ordering while ensuring decoding reliability through non-random placement.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12095476B2Transmitter and parity permutation method thereof
Publication Date: 2024.09.17 SAMSUNG ELECTRONICS CO LTD
  • US12095476B2 patent drawing
  • US12095476B2 patent drawing
  • US12095476B2 patent drawing

AI summary

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to group-wise interleave a plurality of bit groups including the parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups at predetermined positions in the bit groups before the group-wise interleaving are positioned serially after the group-wise interleaving and a remainder of the bit groups before the group-wise interleaving are positioned without an order after the group-wise interleaving so that the puncturer selects parity bits included in the some of the bit groups sequentially and selects parity bits included in the remainder of the bit groups without an order.