LDPC Parity Puncturing for Variable-Length Signaling Robustness
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current channel encoding and modulation techniques for signaling information in broadcast systems lack robustness and efficiency, particularly in next-generation digital broadcasting systems.
Innovation Solution
A parity puncturing apparatus and method that optimizes channel encoding and modulation for signaling information transmission by using a parity puncturing technique with a processor and memory to puncture parity bits from an LDPC codeword, specifically calculating a final puncturing size based on the difference between the LDPC and BCH-encoded bit strings, and applying group-wise interleaving for efficient transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional channel encoding and modulation techniques are used for signaling information transmission, then the system structure remains simple, but the transmission robustness and efficiency deteriorate
Solution Approach 1:
The LDPC codeword is segmented into information bits and parity bits, with the parity bits further divided into multiple groups for selective puncturing. This segmentation allows the system to apply different processing to different parts of the codeword, improving transmission robustness while managing encoding complexity through structured organization of the encoding process
Solution Approach 2:
The patent applies different puncturing strategies to different groups of parity bits based on their importance. Critical parity bits are preserved while less critical ones are punctured, creating local quality variations in the transmitted signal that optimize both robustness and efficiency for signaling information
2Productivity
If all parity bits are transmitted without puncturing, then transmission robustness is improved, but transmission efficiency and resource utilization deteriorate
Solution Approach 1:
The patent extracts and removes (punctures) specific parity bits from the LDPC codeword that are less critical for signaling information transmission. By taking out these redundant bits, the system achieves higher transmission efficiency while maintaining sufficient robustness through the preservation of essential parity bits and the use of BCH outer coding
Solution Approach 2:
The system dynamically adjusts the puncturing rate and pattern based on the specific signaling information being transmitted. By changing the parameter of how many parity bits to puncture and which ones to puncture, the system optimizes the trade-off between transmission efficiency and robustness for different signaling scenarios
3Manufacturing precision
If variable-length signaling information is encoded without optimization, then adaptability to different signal lengths is maintained, but encoding precision and transmission performance deteriorate
Solution Approach 1:
The patent applies preliminary BCH encoding to the signaling information before LDPC encoding. This preliminary action creates a more structured input for the LDPC encoder, improving encoding precision for variable-length signals. The BCH pre-encoding step prepares the data in advance, ensuring that subsequent LDPC processing operates on optimized input regardless of the original signal length
Solution Approach 2:
The system dynamically adapts the encoding parameters, including the number of parity bits to generate and the puncturing pattern, based on the length of the input signaling information. This dynamic adjustment maintains encoding precision across different signal lengths by optimizing the code rate and puncturing rate for each specific case
Data Source
AI summary
A parity puncturing apparatus and method for variable length signaling information are disclosed. A parity puncturing apparatus according to an embodiment of the present invention includes memory configured to provide a parity bit string for parity puncturing for the parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, and a processor configured to puncture a number of bits corresponding to a final puncturing size from the rear side of the parity bit string.


