LDPC Parity Permutation Layout for Sequential Puncturing
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Solution Overview
Problem
Current digital broadcasting systems face challenges in providing improved performance and efficiency in signal transmission and reception, particularly in high-definition digital TV and portable broadcasting, due to limitations in existing transmitter and receiver technologies.
Innovation Solution
A transmitter equipped with a Low Density Parity Check (LDPC) encoder, parity permutator, and puncturer performs parity permutation by group-wise interleaving and puncturing of parity bits, optimizing the order and selection of parity bits for improved decoding performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If parity bits are transmitted in the original order from LDPC encoding, then the transmission process is simple, but decoding performance is insufficient
Solution Approach 1:
The patent applies preliminary action by performing parity permutation before transmission. The transmitter pre-arranges parity bits in a specific order using group-wise interleaving, so that when the receiver gets the signal, the bits are already in an optimal sequence for decoding. This advance preparation improves decoding performance without adding complexity to the receiver side.
Solution Approach 2:
The patent segments the parity bits into multiple groups and applies different permutation patterns to different groups. Specifically, parity bits are divided into first parity bit groups and second parity bit groups, with different interleaving rules applied to each segment. This segmentation allows the system to achieve better decoding performance through structured reorganization without requiring complete reordering of all bits.
2Productivity
If all parity bits are transmitted, then decoding accuracy is maintained, but transmission efficiency decreases due to redundant bits
Solution Approach 1:
The patent applies local quality by treating different parity bit groups differently. Some parity bit groups are permuted while others are not, and certain groups are selected for transmission while others are punctured. This localized differentiation allows the system to maintain decoding accuracy for critical information while reducing transmission of redundant parity bits, thereby improving overall transmission efficiency.
Solution Approach 2:
The patent implements discarding and recovering by selectively puncturing certain parity bit groups that are less critical for decoding. The transmitter removes specific parity bit groups after permutation, reducing the total number of transmitted bits. The receiver can still achieve accurate decoding because the remaining permuted parity bits contain sufficient information, effectively recovering the necessary data with reduced transmission overhead.
3Reliability
If parity bits are permuted to improve decoding performance, then reliability increases, but the complexity of bit arrangement increases
Solution Approach 1:
The patent reduces bit arrangement complexity through segmentation by dividing parity bits into distinct groups with different permutation rules. Instead of applying a complex permutation to all parity bits uniformly, the system segments them into first and second groups, applying simpler, rule-based interleaving to each segment. This modular approach makes the arrangement process more manageable and easier to implement while still achieving the reliability benefits of permutation.
Solution Approach 2:
The patent applies preliminary action by establishing predetermined permutation patterns and rules before transmission. The group-wise interleaving rules are defined in advance, allowing the transmitter to systematically arrange bits without real-time complex calculations. This pre-planned arrangement reduces the computational complexity during actual transmission while maintaining the reliability improvements that permutation provides.
Data Source
AI summary
A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to group-wise interleave a plurality of bit groups including the parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups at predetermined positions in the bit groups before the group-wise interleaving are positioned serially after the group-wise interleaving and a remainder of the bit groups before the group-wise interleaving are positioned without an order after the group-wise interleaving so that the puncturer selects parity bits included in the some of the bit groups sequentially and selects parity bits included in the remainder of the bit groups without an order.