LDPC Parity Sharing Across Sub-Codewords for Smaller Decoders
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Solution Overview
Problem
Large codewords in data processing systems require significant die area and power, leading to complex data decoding circuits that compromise processing performance.
Innovation Solution
Implementing low density parity check encoding systems that combine multiple sub-codewords using a mod 2 mathematical process to create a composite codeword, allowing for reduced circuit size and power consumption while maintaining high error correction capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large codewords are used to achieve increased data processing performance, then processing performance is improved, but data decoding circuit size and power consumption increase significantly
Solution Approach 1:
The patent divides a large codeword into multiple smaller sub-codewords that can be processed independently by separate decoding circuits. This segmentation allows the system to achieve large codeword processing performance while using multiple smaller, more manageable decoding circuits that consume less power and occupy less die area than a single large decoding circuit would require.
2Productivity
If large codewords are used to achieve increased data processing performance, then processing performance is improved, but data decoding circuit power consumption increases significantly
Solution Approach 1:
The patent segments the decoding function into multiple independent circuits processing smaller sub-codewords. This approach reduces the power consumption of individual decoding circuits compared to a single large decoding circuit, while the combined performance of multiple circuits achieves the desired overall processing performance.
3Area of stationary object
If smaller codewords are used to reduce data decoding circuit size and power, then circuit size and power are reduced, but data processing performance decreases
Solution Approach 1:
The patent combines multiple smaller decoding circuits that process sub-codewords to achieve the equivalent performance of a single large decoding circuit. By merging the outputs of multiple smaller circuits through mathematical combination operations, the system attains high data processing performance while maintaining the advantages of smaller individual circuit components.
4Use of energy by stationary object
If smaller codewords are used to reduce data decoding circuit power consumption, then power consumption is reduced, but data processing performance decreases
Solution Approach 1:
The patent merges the processing results from multiple smaller decoding circuits that operate on sub-codewords. Through mathematical combination operations, the system achieves high overall data processing performance while each individual circuit consumes less power than a single large decoding circuit would require.
Data Source
AI summary
Various embodiments of the present invention provide systems and methods for data processing. For example, a low density parity check encoding system is described that includes: a low density parity check encoder circuit, and a combining circuit. The low density parity check encoder circuit is operable to encode a first data set to yield a first low density parity check encoded sub-codeword, and to encode a second data set to yield a second low density parity check encoded sub-codeword. The combining circuit is operable to: generate a composite low density parity check sub-codeword by mathematically combining at least the first low density parity check encoded sub-codeword and the second low density parity check encoded sub-codeword; and combine at least the first low density parity check encoded sub-codeword and the composite low density parity check sub-codeword into an overall codeword.