LDPC Parity Unit Circuit for Pipelined Check Node Processing
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Solution Overview
Problem
Designing simpler circuits for check nodes (parity units) in parallel, pipelined LDPC decoders that compute parity using the parity check matrix is a complex challenge.
Innovation Solution
A parity unit circuit is introduced, comprising three logic blocks: a memory logic block for data storage, a first compute logic block for computing parity messages and their signs, and a second compute logic block for updating data for the next iteration, allowing for high performance while minimizing area utilization on the integrated circuit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If complex circuits are used for check nodes in parallel LDPC decoders to achieve high performance, then processing speed and reliability are improved, but area utilization increases
Solution Approach 1:
The parity unit circuit is divided into three distinct logic blocks: memory logic block for data storage, first compute logic block for computing final parity message values, and second compute logic block for computing new values for next iteration. This segmentation allows each block to be optimized independently, achieving high processing speed while controlling area utilization through efficient resource distribution.
Solution Approach 2:
The circuit implements dynamic operation by using the same memory logic block for both current and next iteration data storage, and by having compute blocks that switch between computing final values and computing new values for the next iteration. This dynamic reuse of resources reduces the total area required while maintaining high processing throughput through pipelined operation.
2Area of stationary object
If simpler circuits are used for check nodes to reduce area utilization, then area efficiency is improved, but processing performance deteriorates
Solution Approach 1:
The memory logic block serves multiple functions: storing data for the current iteration and storing data for the next iteration. The compute logic blocks are designed to compute both final parity message values for current iteration and new values for the next iteration. This multi-functionality reduces the total circuit area while maintaining processing throughput by eliminating redundant dedicated storage and computation units.
Solution Approach 2:
The circuit performs preliminary computation by calculating new values for the next iteration in the second compute logic block while the first compute logic block is computing final values for the current iteration. This preliminary action enables pipelined operation where next iteration computations are prepared in advance, maintaining high processing speed without requiring additional dedicated hardware for each iteration.
Data Source
AI summary
A parity unit circuit for use in a parallel, pipelined, low density parity check (LDPC) decoder that implements an iterative, min-sum, message passing LDPC algorithm. The parity unit provides a memory logic block for storing information relating to a current and next iteration of the LDPC computations and includes a “compute 1” logic block for computing a parity message (with sign) for application to related bit nodes and a “compute2” logic block for updating the data stored in the memory logic block for a next iteration of the LDPC decoder.