LDPC Encoder PCM-Based Parity Updates for Co-Channel Interference

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Solution Overview

Problem

Current LDPC codes for terrestrial broadcasting face challenges in spectrum efficiency due to co-channel interference, particularly in areas where frequency reuse is limited by white spaces, and existing codes do not provide specific encoding methods suitable for DVB broadcast standards.

Innovation Solution

A new LDPC codeword of lengths 64800 or 16200, with an efficient method for updating parity bit addresses using a sequence corresponding to a parity check matrix, enabling improved LDPC encoding by incorporating a systematic part, a first parity part from a dual diagonal matrix, and a second parity part from an identity matrix, facilitating better interference handling and spectrum reuse.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional LDPC codes are used for terrestrial broadcasting, then basic error correction is provided, but spectrum efficiency deteriorates due to white spaces caused by co-channel interference

Engineering Contradiction:

Improveerror correction capabilityVSAvoidspectrum efficiency

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent modifies the parity check matrix structure by dividing it into sub-matrices with specific patterns (dual diagonal and identity matrices), changing the structural parameters of the LDPC code to achieve both error correction and spectrum efficiency

Inventive Principle:

Principle #35Parameter changes

2Loss of energy

If frequency reuse is implemented to improve spectrum efficiency, then white spaces are eliminated, but co-channel interference increases making signal demodulation difficult

Engineering Contradiction:

Improvespectrum efficiencyVSAvoidco-channel interference

Core Design Contradiction:

Loss of energyVSObject-affected harmful factors

Solution Approach 1:

The parity check matrix is segmented into multiple sub-matrices (H1, H2, H3, H4) with different structural patterns, allowing the system to handle overlapping signals by processing different portions of the codeword with different matrix structures

Inventive Principle:

Principle #1Segmentation

3Ease of manufacture

If existing LDPC codes are used, then encoding can be performed, but no specific encoding method is provided for DVB broadcast standards requiring code lengths of 64800 or 16200

Engineering Contradiction:

Improveencoding capabilityVSAvoidcompatibility with DVB standards

Core Design Contradiction:

Ease of manufactureVSAdaptability or versatility

Solution Approach 1:

The patent provides a universal encoding method that works for both code lengths (64800 and 16200) by using the same dual diagonal matrix and identity matrix structures, making it adaptable to different DVB broadcast standards

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Productivity

If parity bit addresses are updated without optimization, then encoding can be completed, but encoding efficiency is reduced

Engineering Contradiction:

Improveencoding efficiencyVSAvoidparity bit address update time

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The patent pre-defines the parity check matrix structure with dual diagonal and identity matrices, allowing parity bit addresses to be calculated systematically rather than randomly, which speeds up the encoding process

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS10419159B2Low density parity check encoder, and low density parity check encoding method using the same

Publication Date: 2019.09.17 ELECTRONICS & TELECOMM RES INST

AI summary

A low density parity check (LDPC) encoder, an LDPC decoder, and an LDPC encoding method are disclosed. The LDPC encoder includes first memory, second memory, and a processor. The first memory stores an LDPC codeword. The second memory is initialized to 0. The processor generates the LDPC codeword by performing accumulation with respect to the second memory using information bits. The accumulation is performed at parity bit addresses that are updated using a sequence corresponding to a parity check matrix (PCM).