LDPC Bit Interleaver Permutation for 256-Symbol Burst Error Distribution

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Solution Overview

Problem

Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation unless burst errors in digital broadcast channels are appropriately distributed, necessitating an optimized bit interleaver design tailored to the modulation order and error correction code parameters.

Innovation Solution

A bit interleaver is designed for an LDPC coder with a length of 64800 and a code rate of 3/15, using a 256-symbol mapping modulator, which interleaves the LDPC codeword on a bit group basis according to a specific permutation order, effectively distributing burst errors and optimizing performance for next-generation broadcasting systems like ATSC 3.0.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a bit interleaver is designed for specific modulation order and code parameters, then performance is optimized for those parameters, but adaptability to other configurations is reduced

Engineering Contradiction:

ImproveperformanceVSAvoidadaptability

Core Design Contradiction:

ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent applies parameter changes by deriving the bit interleaver specifically optimized for 256-symbol mapping (modulation order) and LDPC code rates of 3/15, 5/15, and 7/15 with codeword length 64800. The interleaver structure, including bit group size and permutation patterns, is tailored to these specific parameters to maximize performance while maintaining reliability under the designated configuration.

Inventive Principle:

Principle #35Parameter changes

2Reliability

If burst errors are distributed through bit interleaving, then error correction performance is improved, but device complexity increases

Engineering Contradiction:

Improveerror correction performanceVSAvoidinterleaver structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies segmentation by dividing the LDPC codeword into multiple bit groups before interleaving. Each bit group contains a specific number of bits (determined by the parallel factor), and the interleaver operates on these segmented groups using permutation patterns. This segmentation approach effectively distributes burst errors across different bit groups while maintaining a manageable interleaver structure that can be implemented with reasonable complexity.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS10541709B2Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 256-symbol mapping, and bit interleaving method using same

Publication Date: 2020.01.21 ELECTRONICS & TELECOMM RES INST

AI summary

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.