LDPC Bit Interleaver Permutation for 256-Symbol Burst Error Spreading
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems face rapid performance degradation due to burst errors in digital broadcast channels, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver is designed for an LDPC coder with a length of 64800 and code rate of 4/15, using a specific permutation order for bit group-based interleaving, optimized for 256-symbol mapping, to effectively distribute burst errors and enhance error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional bit interleaver is used in BICM systems, then the system structure remains simple, but burst errors in digital broadcast channels cause rapid performance degradation
Solution Approach 1:
The patent segments the 64800-bit LDPC codeword into multiple bit groups of 360 bits each (180 groups total). This segmentation allows the interleaver to process and distribute burst errors more effectively by treating each bit group as a manageable unit, resolving the contradiction between maintaining simple structure and achieving reliable error correction.
Solution Approach 2:
The patent optimizes the interleaver design by changing key parameters: setting the block size to 360 bits (matching the LDPC parallel factor), defining specific permutation patterns for bit group reordering, and configuring the interleaver depth to match the modulation order. These parameter changes enable the interleaver to achieve high reliability for 256-QAM modulation with LDPC(64800, 4/15) coding without excessive complexity.
2Reliability
If the bit interleaver is optimized for specific modulation order and code parameters, then error correction performance is maintained, but the system loses flexibility in adapting to different configurations
Solution Approach 1:
The patent employs parameter changes by making the interleaver configuration adaptable through defined relationships: the block size is set to the LDPC parallel factor (360), the number of groups is derived from codeword length divided by block size (64800/360=180), and permutation patterns are optimized for 256-QAM. This allows the same interleaver structure to be adapted to different modulation orders and code rates by adjusting these parameters, maintaining both reliability and flexibility.
3Reliability
If burst errors are not distributed, then the interleaver structure remains simple, but performance degrades rapidly in digital broadcast channels
Solution Approach 1:
The patent divides the codeword into 180 bit groups of 360 bits each, then applies permutation reordering to these groups. This segmentation approach distributes burst errors across different bit groups rather than concentrating them, achieving reliable error correction performance while keeping the interleaver structure manageable through systematic grouping and permutation.
Solution Approach 2:
The patent introduces a new dimension of organization by arranging bits in a two-dimensional structure (groups × positions within groups) and applying permutation across the group dimension. This dimensional approach to interleaving effectively disperses burst errors while maintaining a structured, implementable design that doesn't require overly complex processing.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 4/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.