LDPC Bit Interleaver Permutation for 256-Symbol Burst Error Distribution
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Solution Overview
Problem
Bit-Interleaved Coded Modulation (BICM) systems suffer from rapid performance degradation due to burst errors in digital broadcast channels unless burst errors are appropriately distributed, necessitating an optimized bit interleaver design for modulation order and error correction code parameters.
Innovation Solution
A bit interleaver optimized for an LDPC coder with a length of 16200 and a code rate of 10/15, using 256-symbol mapping, which interleaves the LDPC codeword on a bit group basis with a parallel factor of 360, employing a specific permutation order to effectively distribute burst errors and improve error correction performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a bit interleaver is used to distribute burst errors in BICM systems, then error correction performance is improved, but device complexity increases due to the need for optimized interleaver design matching specific modulation order and error correction code parameters
Solution Approach 1:
The patent applies parameter changes by designing the bit interleaver with specific parameters matched to the LDPC code length (16200), code rate (10/15), and modulation order (256-QAM). The interleaver uses a parallel factor of 360 and processes data in bit groups of 360 bits, with a specific number of interleaving stages (e.g., 5 stages) and stage-specific parameters (e.g., stage shift amounts). By optimizing these parameters for the specific system configuration, the interleaver achieves effective burst error distribution without requiring overly complex adaptive mechanisms.
2Reliability
If the bit interleaver is optimized for specific LDPC coder parameters and modulation schemes, then performance degradation from burst errors is prevented, but adaptability to different broadcasting standards is reduced
Solution Approach 1:
The patent applies segmentation by dividing the LDPC codeword into multiple bit groups, where each group contains a specific number of bits (e.g., 360 bits corresponding to the parallel factor). The bit interleaver processes each bit group independently through multiple interleaving stages, applying different permutation patterns to different groups. This segmented approach allows the interleaver to be designed for specific parameters while maintaining a structured framework that can be adapted to different coding schemes by adjusting the number of groups and stage parameters.
Data Source
AI summary
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.